CMOS Digital Integrated Circuits Lec 12 Dynamic Logic

CMOS Digital Integrated Circuits Lec 12 Dynamic Logic Circuits 1 CMOS Digital Integrated Circuits

Dynamic Logic Circuits n Goals Understand • • • 2 Pass transistors circuits Voltage bootstrapping Synchronous dynamic circuit techniques Dynamic CMOS circuit techniques High-performance dynamic CMOS circuits CMOS Digital Integrated Circuits

Static v. s. Dynamic n Static Logic Gates • Valid logic levels are steady-state operating points • Outputs are generated in response to input voltage levels after a certain time delay, and it can preserve its output levels as long as there is power. • All gate output nodes have a conducting path to VDD or GND, except when input changes are occurring. n Dynamic Logic Gates • The operation depends on temporary storage of charge in parasitic node capacitances. • The stored charge does not remain indefinitely, so must be updated or refreshed. This requires establishment of an update or recharge path to the capacitance frequently enough to preserve valid voltage levels. 3 CMOS Digital Integrated Circuits

Static v. s. Dynamic (Continued) n Advantages of Dynamic Logic Gates • Allow implementation of simple sequential circuits with memory functions. • Use of common clock signals throughout the system enables the synchronization of various circuit blocks. • Implementation of complex circuits requires a smaller silicon area than static circuits. • Often consumes less dynamic power than static designs, due to smaller parasitic capacitances. 4 CMOS Digital Integrated Circuits

Pass-Transistor Latch Circuit and Operation Soft note D MP X ML Q Vx Cx Q MD CK n Operation • CK = H, D=H or L : CX is charged up or down through MP, and X becomes H or L (depends on D input) since MP is on D and X are connected. • CK = L: X is unchanged since MP is off and CX is isolated from D, and the charge is stored on capacitances CX. • For X = H, Q = L and Q = H • For X = L, Q = H and Q = L n 5 Cost: 3 to 5 devices (very low) CMOS Digital Integrated Circuits

Pass-Transistor Latch Soft Node Concept • During CK = 1: Let D = 1, i. e. VD = VOH = VDD MP is conducting and charges CX to a “weak 1” (VX = VDD – VTD) Q = L (VQ<VTD) and Q = H(VQ=VDD). • During CK = 0: Logic-level VX is preserved through charge storage on CX. However, VX starts to drop due to leakage. • What value does VX have to deteriorate to no longer like a stored ? Example (see p 359~359, Kang and Leblebici): For an inverter with VDD = 5 V, VT, n = 0. 8 V , VOL = 2. 9 V and VIH = 2. 9 V, initial VX =4. 2 V. But due to leakage currents, this will decline over time. When it declines below VIH(2. 9 V), then a logic 0 out of the inverter can no longer guaranteed. Thus, to avoid an erroneous output, the charge stored in CX must be restored or refreshed to its original level before VX declines below 2. 9 V. 6 CMOS Digital Integrated Circuits

Basic Principles of Pass Transistor Circuits Logic “ 1” Transfer n Logic “ 1” Transfer: VX(t=0)=0 V, Vin=VOH=VDD, CK=0 VDD Soft note Vin MP Vx X Cx CK Vin=VDD D S MP ID Vx X Cx CK • VGS = VDD - VX, VDS = VDD - VX = VGS. • Therefore, VDS> VGS – VT, MP MP is in saturation. • Note that the VT, MP is subject to substrate bias effect and therefore, depends on the voltage level VX. We will neglect the substrate bias effect for simplicity. 7 CMOS Digital Integrated Circuits

Basic Principles of Pass Transistor Circuits Logic “ 1” Transfer (Cont. ) • Integrating the above equation with t from 0 t and VX from 0 VX, we have • Therefore, • and, 8 CMOS Digital Integrated Circuits

Basic Principles of Pass Transistor Circuits Logic “ 1” Transfer (Cont. ) VX Vmax=VDD-VT, MP t 0 • VX rises from 0 V and approaches a limit value Vmax = VX(t)|t= = VDDVT, MP, but it can not exceed this value, since the pass transistor will turn off at this point (VGS=VT, MP). Therefore, it transfers a “weak logic 1”. • The actual Vmax by taking the body effect into account is, • and tcharge = time to VX = 0. 9 Vmax, • Body Effect: Reduce VX, and Increase tcharge 9 CMOS Digital Integrated Circuits

Basic Principles of Pass Transistor Circuits Logic “ 0” Transfer n Logic “ 0” Transfer: VX(t=0)=Vmax= VDD – VT, MP, Vin=VOL=0 V, CK= 0 VDD Soft note Vin MP Vx X Cx CK Vin=0 S D MP ID Vx X Cx CK • VGS = VDD, VDS = Vmax = VDD – VT, MP. • Therefore, VDS VGS – VT, MP MP is in linear region. • Note that the VSB=0. Hence, there is no body effect for MP (VT, MP= VT 0, MP). But the initial condition VX(t=0)=VDD – VT, MP contains the threshold voltage with body effect. To simplify the expressions, we will use VT, MP in the following. 10 CMOS Digital Integrated Circuits

Basic Principles of Pass Transistor Circuits Logic “ 0” Transfer (Cont. ) • Integrating the above equation with t from 0 t and VX from VT, MP VX, we have • Therefore, • and, 11 CMOS Digital Integrated Circuits

Basic Principles of Pass Transistor Circuits Logic “ 0” Transfer (Cont. ) • VX drops from Vmax = VDD-VT, MP, to 0 V. Hence, unlike the chargeup case, it transfers a “strong logic 0”. • fall = time of VX drops from 0. 9 Vmax to 0. 1 Vmax, VX Vmax=VDD-VT, MP • where, t 0 12 CMOS Digital Integrated Circuits

Basic Principles of Pass Transistor Circuits Charge Storage and Charge Leakage • At t = 0, CK=0, VX= Vmax, Vin =0. The charge stored in CX will gradually leak away, primarily due to the leakage currents associated with the pass transistor. The gate current of the inverter driver transistor is negligible. Vin =0 MP Ileakage Vx Igate=0 Cx CK=0 VCK=0 Ileakage Vin=0 n+ p-type Si 13 Isubthreshold n+ VX CX Ireverse CMOS Digital Integrated Circuits

Basic Principles of Pass Transistor Circuits Charge Storage and Charge Leakage (Cont. ) VCK=0 Ileakage VX Vin=0 n+ Isubthreshold Ireverse p-type Si Ileakage= Isubthreshold + Ireverse Ileakage Isubthreshold CX n+ Ireverse Vx Cj(VX) Cin= Cgb + Cpoly + Cmetal Cin CX= Cin + Cj Drain-substrate pn-junction • • 14 Isubthreshold is the subthreshold current for the pass transistor with CK=0. Ireverse is the reverse current for the source/drain pn junction at node X Cj (VX) : due to the reverse biased drain-substrate junction, a function of VX Cin: due to oxide-related parasitics, can be considered constants. CMOS Digital Integrated Circuits

Basic Principles of Pass Transistor Circuits Charge Storage and Charge Leakage (Cont. ) Ileakage= Isubthreshold + Ireverse Ileakage Vx Cin= Cgb + Cpoly + Cmetal Isubthreshold Ireverse Cj Cin CX= Cin + Cj Drain-substrate pn-junction • The total charge stored in the soft node can be expressed as, Q = Qj (VX) + Qin where Qin = Cin • VX • The total leakage current can be expressed as the time derivative of the total soft-node charge Q 15 CMOS Digital Integrated Circuits

Basic Principles of Pass Transistor Circuits Charge Storage and Charge Leakage (Cont. ) • Where • Therefore, • We have to solve the above differential equation to estimate the actual charge leakage time from the soft node. 16 CMOS Digital Integrated Circuits

Basic Principles of Pass Transistor Circuits Charge Storage and Charge Leakage (Cont. ) n A quick estimate of the worst-case leakage behavior • Assume that the minimum combined soft-node capacitance is CX, min = Cgb + Cpoly + Cmental + Cdb, min is the minimum junction capacitance, obtained when VX=Vmax • The worst-case holding time (thold) is the shortest time for VX to drop from its initial logic-high value to the logic threshold voltage due to leakage. thold = Qcritical, min/Ileakage, max Vth • where Qcritical, min =CX, min (Vmax-VDD/2) 17 CMOS Digital Integrated Circuits

Basic Principles of Pass Transistor Circuits Charge Storage and Charge Leakage (Cont. ) n Example 9. 2: Consider the soft-node structure shown below, which consists of the drain (or source, depending on current direction) terminal of the pass transistor, connected to the polysilicon gate of an n. MOS driver transistor via a metal interconnect. Question: is to estimate thold if VDD=5 V and the soft-node is initially charged to Vmax. Vx MP M 1 Cx CK soft node 3 1 MP 4 1 6 CK diffusion 18 5 5 6 2 2 3 M 1 2 4 1 metal polysilicon CMOS Digital Integrated Circuits

Basic Principles of Pass Transistor Circuits Charge Storage and Charge Leakage (Cont. ) • Material parameters: VTO = 0. 8 V = 0. 4 V 1/2 |2 F| = 0. 6 V 0 = 0. 88 V 0 SW = 0. 95 V Ileakage, max = 0. 85 p. A COX = 0. 065 f. F/ m 2 C’metal = 0. 036 f. F/ m 2 C’poly = 0. 055 f. F/ m 2 Cj 0 = 0. 095 f. F/ m 2 Cj 0 SW = 0. 2 f. F/ m 3 1 MP 4 1 6 5 diffusion metal polysilicon Soft-node Capacitance Calculation CK 2 2 3 M 1 4 1 • Oxide-related (constant) parasitic capacitances » Cgb = COX·W·Lmask = 0. 065 f. F/ m 2· (4 m 2 m) = 0. 52 f. F » Cmetal = C’metal·W·Lmetal = 0. 036 f. F/ m 2· (5 m 5 m) = 0. 90 f. F » Cploy = C’poly·W·Lpoly = 0. 055 f. F/ m 2· (36+6+2 m 2) = 2. 42 f. F 19 CMOS Digital Integrated Circuits 2

Basic Principles of Pass Transistor Circuits Charge Storage and Charge Leakage (Cont. ) • Parasitic junction capacitance By zero-bias unit capacitance values in the previous slide, we have » Cbottom = Abottom·Cj 0 = 0. 095 f. F/ m 2· (36 m 2 + 12 m 2 ) = 4. 56 f. F » Csidewall = Cj 0 SW·Psidewall = 0. 2 f. F/ m 2· (30 m) = 6. 00 f. F Therefore » Cdb, max = Cbottom + Csidewall = 4. 56 f. F + 6. 00 f. F = 10. 56 f. F The minimum drain junction capacitance is achieved as the junction is biased with Vmax. We need to find Vmax to determine Cdb, min » Vmax = 5. 0 - 8. 0 - 0. 4 ( 0. 6+ Vmax - 0. 6 ) Vmax = 3. 68 V Therefore, 20 CMOS Digital Integrated Circuits

Basic Principles of Pass Transistor Circuits Charge Storage and Charge Leakage (Cont. ) • Combining the Oxide-related (constant) parasitic capacitances with the parasitic junction capacitance, CX, min can be got as CX, min = Cgb + Cpoly + Cmental + Cdb, min = 0. 52 + 2. 42 + 0. 90 +4. 71 = 8. 55 f. F • The amount of the critical charge drop is Qcritical = CX, min(VX, min-VDD/2)=8. 55 (3. 68 -2. 5)=10. 09 f. C • Finally, thold = Qcritical /Ileakage, max=11. 87 ms • The worst-case hold time for this structure is relatively long, even with a very small soft-node capacitance of 8. 55 f. F. It means that the logic gate can be preserved in a soft node for a long time period when the leakage current is small. 21 CMOS Digital Integrated Circuits

Voltage Bootstrapping • The Voltage bootstrapping is a technique to overcome threshold voltage drops of the output voltage levels in pass transistor gates or enhancement-load inverters and logic gates. • Consider the following circuit with VX VDD M 2 is in saturation. If Vin is low, the maximum output voltage is limited as Vout(max) = VX – VT 2(Vout) VDD Vx M 2 Vout Vin 22 M 1 Cout CMOS Digital Integrated Circuits

Voltage Bootstrapping (Cont. ) • To overcome the voltage drop, the voltage VX must be increased. This can be achieved by adding a third transistor M 3 into the circuit. » CS and Cboot represent the capacitances which dynamically couple VX to the ground and to the output. » The goal of the above circuit is to provide a high enough voltage VX to let Vout go to VDD instead of VDD-VT 2(Vout). VDD M 3 Vx CS M 2 Cboot Vout Vin M 1 Cout • Initially, let Vin=H M 1 and M 2 are on, and Vout=L. • Now Vin goes to L M 1 turns off, and Vout starts to rise. This change will be coupled to VX through the bootstrap capacitor, Cboot. 23 CMOS Digital Integrated Circuits

Voltage Bootstrapping (Cont. ) • Let i. Cboot be the transient current through Cboot during the charge-up event, and let i. CS be the current through CS. Assume i. CS i. Cboot, we have i. CS i. Cboot CS·d. VX/dt Cboot·d(Vout-VX)/dt (CS+Cboot)·d. VX/dt Cboot·d. Vout/dt d. VX/dt Cboot /(CS+Cboot) ·d. Vout/dt • This expression can be integrated to give VX such that Vout will rise to VDD. • If Cboot >> CS, then for Vout rising to VDD, VX(max) 2 VDD – VT 3 – VOL > VDD – VT 2. for realistic values of the voltages. Thus, it is feasible to use the circuit to obtain Vout =VDD. 24 CMOS Digital Integrated Circuits

Voltage Bootstrapping (Cont. ) • To overcome threshold voltage drop at Vout, the minimum VX is VX(min) = VDD + VT 2|Vout = VDD = [VDD-VT 3(VX)]+Cboot /(CS+Cboot) ·(VDD-VOL) • Therefore, the required capacitance ratio Cboot /(CS+Cboot) is • CS is the sum of the parasitic source-to-substrate capacitance of M 3 and the gate-to-substrate capacitance of M 2. 25 CMOS Digital Integrated Circuits

Voltage Bootstrapping (Cont. ) • Cboot can be specifically constructed to control its value by using a transistor with the source and drain connected together at Vout and the gate attached to VX. Since its drain and source tied together, it simply acts as an MOS capacitor between VX and Vout. VDD M 3 Vx M 2 Cboot Vout Vin M 1 • See Kang and Leblebici at pp. 373 for a SPICE example. 26 CMOS Digital Integrated Circuits

Synchronous Dynamic Circuit Techniques – Dynamic Pass Transistor Circuits • The multi-stage synchronous circuit is shown below. The circuit consists of cascaded combinational logic stages interconnected through n. MOS pass transistors. Its operation depends on temporary charge storage in the parasitic input capacitances. Comb. Logic 2 Comb. Logic 1 A B 1 2 C D Comb. Logic 3 F 1 F 2 1 1 2 t phase 1 phase 2 t 1, 2 non-overlapping clocks • Logic levels are stored on input capacitances during the inactive clock phase. 27 CMOS Digital Integrated Circuits

Dynamic Pass Transistor Circuits Two-Phase Clock Dynamic Shift Register n Depletion-Load Dynamic Shift Register • The max clock frequency is determined by signal propagation delay through one inverter stage. • One half-period of the clock signal must be long enough to allow Cin to charge up or down, and Cout to charge to the new value. • The logic-high input value is one VT 0 lower than VDD 1 Vin 28 VDD 2 Cin 1 Cout 1 VDD 1 Cin 2 Cout 2 Vout Cin 3 Cout 3 CMOS Digital Integrated Circuits

Dynamic Pass Transistor Circuits Enhancement-Load Dynamic Shift Register n Enhancement-Load Dynamic Shift Register 1 • Instead of biasing load transistors with a constant gate voltage, a clock signal is applied to the gate of the load transistor power dissipation and silicon area are reduced. • The power supply current flows only when the load devices are activated by the clock signal, the power consumption is lower than the depletionload n. MOS logic. VDD 1 VDD 2 Vout Vin 29 Cin 1 Cout 1 Cin 2 Cout 2 Cin 3 Cout 3 CMOS Digital Integrated Circuits

Enhancement-Load Dynamic Shift Register 1 (Cont. ) General Structure VDD 2 1 1 Z A B C n. MOS Logic Stage 1 D n. MOS Logic Stage 2 General Circuit Structure of Ratioed Synchronous Dynamic Circuit 30 CMOS Digital Integrated Circuits

Enhancement-Load Dynamic Shift Register 1 (Cont. ) VDD 1=H 1 2 Vout 1 Vin VDD 2=H Cin 2 Cin 1 2 2 Cout 1 Vout 3 Cout 2 VOL VDD 1 Vout 1 Vin 1 VDD Vout 2 Cout 1 Cin 1 1 VDD Cin 3 Cout 3 VDD 2 Vout 2 Cin 2 Cout 2 Vout 1 VOL Vout 3 Cin 3 Cout 3 VOL • VOL → kdriver/kload Ratioed Dynamic Logic. • Cout 1, Cin 2 & Cout 2, Cin 3 interact Charge Sharing 31 CMOS Digital Integrated Circuits

Enhancement-Load Dynamic Shift Register 2 n Enhancement-Load Dynamic Shift Register 2 • The input pass transistor and the load transistor are driven by the same clock phase. • The valid low-output voltage level VOL=0 V can be achieved regardless of the driver-to-load ratio, this circuit is a ratioless dynamic logic. VDD 1 VDD 2 1 VDD Vout Vin 32 Cin 1 Cout 1 Cin 2 Cout 2 Cin 3 Cout 3 CMOS Digital Integrated Circuits

Enhancement-Load Dynamic Shift Register 2(Cont. ) General Structure 1 VDD 2 Z A B C n. MOS Logic Stage 1 D n. MOS Logic Stage 2 General Circuit Structure of Ratioless Synchronous Dynamic Circuit 33 CMOS Digital Integrated Circuits

Enhancement-Load Dynamic Shift Register 2 (Cont. ) VDD 1=H VDD 2 1 Vout 1 Vin Cin 1 1 Cout 1 Cin 2 2 Cin 1 Cout 1 Vout 1 0 V Vout 3 Cin 3 Cout 2 Cout 3 VOL VDD Vout 2 0 V VDD 1 Vout 1 Vin 1 Vout 2 Vout 1 VOL VDD 2=H VDD Vout 2 Cin 2 Vout 3 Cin 3 Cout 2 VOL Cout 3 Vout 3 0 V • VOL → 0 V Ratioless Dynamic Logic. • Cini << Couti-1 for i=2, 3 Minimum Charge Sharing 34 CMOS Digital Integrated Circuits

Enhancement-Load Dynamic Shift Register 2 (Cont. ) Charge Sharing 2 Vb Va Cout 1 Cin 2 Charge Sharing • 2 = 0: Qout 1 = Cout 1 Vb and Qin 2 = Cin 2 Va • 2 = 1: Qtotal = Cout 1 Vb + Cin 2 Va and Ctotal = Cout 1 + Cin 2 The resulting voltage across Ctotal is VR = Qtotal / Ctotal = (Cout 1 Vb + Cin 2 Va )/ (Cout 1 + Cin 2) • If Vb = VDD and Va << Vb VR Cout 1 VDD /(Cout 1 + Cin 2) VR VDD if Cin 2 << Cout 1 35 CMOS Digital Integrated Circuits

Dynamic CMOS Transmission Gate Logic • Each transmission gate is controlled by the clock signal and its complement. Therefore, the two-phase clocking need four clock signals. • As in the n. MOS structures, the CMOS dynamic circuit relies on charge storage in parasitic input capacitances during the inactive clock cycles. 1 2 1 A B F 1 Stage 1 C Stage 2 D 1 1 36 2 CMOS Digital Integrated Circuits

Dynamic CMOS Transmission Gate Logic Shift Register • The basic building block of the shift register consists of a CMOS inverter, which is driven by a TG. • CK=1 Vin is transferred onto the parasitic input capacitance CX. • The low on-resistance of TG results in » A smaller transfer time compared to n. MOS-only switches. » No threshold voltage drop across TG soft node VDD CK VX Vin CK 37 CX Vout Cy CMOS Digital Integrated Circuits

Dynamic CMOS Transmission Gate Logic Shift Register (Cont. ) • The single-phase CMOS shift register is built by » Cascading identical inverter units » Driving each stage alternately with the CK and CK. • Ideally: The odd-numbered stages are on as CK=1, while the evennumbered stages are off the cascaded inverter stages are alternately isolated. • Practically: » The CK and CK are not a truly nonoverlapping signal pair, since their waveforms have finite rise and fall times. » One of the signals is generated by inverting the other the clock skew is unavoidable. » True two-phase clocking is preferred over single-phase clocking. CK CK V 1 V 2 CK 38 CK V 3 CK V 4 CK CMOS Digital Integrated Circuits

Dynamic CMOS Precharge-Evaluate Logic Reduced Transistor Count VDD Mp Vout C inputs n. MOS Logic Internal capacitance Me Vout • =0 C precharges to VDD (output is not available during precharge) • =1 C selectively discharges to 0 (output is only available after discharge is complete) evaluate precharge t t 39 CMOS Digital Integrated Circuits

Dynamic CMOS Precharge-Evaluate Logic An Example VDD Mp Vout A 1 B 1 A 2 B 2 A 3 Me Z is high when =0 Z=(A 1 A 2 A 3 +B 1 B 2) 40 CMOS Digital Integrated Circuits

Dynamic CMOS Precharge-Evaluate Logic Advantages/Disadvantages n Advantages • • • n Need only N+2 transistors to implement a N-input gate. Low static power dissipation No DC current paths to place constraints on device sizing Input capacitance is same as pseudo n. MOS gate. Pull-up time is improved by active switch to VDD. Disadvantages • The available time of output is less than 50 % of the time. • Pull-down time is degraded due to series active switch to 0. • Logic output value can be degraded due to charge sharing with other gate capacitances connected to the output. • Minimum clock rate determined by leakage on C. • Maximum clock rate determined by circuit delays. • Input can only change during the precharge phase. Inputs must be stable during evaluation; otherwise an incorrect value on an input could erroneously discharge the output node. (single phase P-E logic gates can not be cascaded) • Outputs must be stored during precharge, if they are required during the next evaluate phase. 41 CMOS Digital Integrated Circuits

Dynamic CMOS Precharge-Evaluate Logic Cascading Problem VDD Mp 1 Vout 1 inputs 1 st stage n. MOS Logic Me 1 Mp 2 Vout 2 2 nd 1 Me 2 precharge evaluate Vout t Vout 1 does not switch from “ 1” to “ 0” fast enough t correct state erroneous state t • Evaluate: » Me 1, Me 2 ON » Mp 1, Me 2 OFF • Problem: All stages must evaluate simultaneously one clock does not permit pipelining of stages. 42 CMOS Digital Integrated Circuits

High Performance Dynamic CMOS Circuits Domino CMOS Logic VDD Static inverter serves to buffer the logic part of the circuit from its output load X inputs Vout n. MOS Logic • =0 » X precharges to VDD, and Vout = 0. • =1 » X remains high, and Vout remains low. » X discharges to 0, and Vout changes from 0 to 1. precharge evaluate 1 t 43 CMOS Digital Integrated Circuits

VDD Domino CMOS Logic VDD X 1 inputs X 1 X 2 X 3 n. MOS Logic evaluate X 2 n. MOS Logic X 3 n. MOS Logic evaluate precharge teval t t t Max number gates limited: total propagation delay < teval t 44 CMOS Digital Integrated Circuits

Domino CMOS Logic (Cont. ) VDD VDD X 1 inputs n. MOS Logic X 3 X 2 n. MOS Logic • The problem in cascading conventional dynamic CMOS occurs when one or more inputs make a 1 to 0 transition during evaluation. • Domino circuits can fix the above problem » During the evaluation, each buffer output can make at most one transition (from 0 to 1), and thus each input of all subsequent logic stages can also make at most one (0 to 1) transition. 45 CMOS Digital Integrated Circuits

Domino CMOS Logic The Limitations • The static CMOS and domino gates can be used together, see Fig. 9. 31. in Kang and Leblebici. The limitation: the number of inverting static logic stages in cascade must be even, to let the inputs of next domino stage can have only 0 to 1 transitions during the evaluation. • Can implement only non-inverting logic • Due to precharge use, can suffer from charge sharing during the evaluation which may cause erroneous outputs. » The problem will be described in the next slide, and several solutions will be presented later. 46 CMOS Digital Integrated Circuits

Domino CMOS Logic Charge Sharing VDD VX Vout C 1 N C 2 VX = VDDC 1/(C 1+C 2) Keep C 2 << C 1 • Assume that all inputs are low initially, and the voltage across C 2=0 V • During the precharge, C 1 is charged to VDD • If transistor N switches from 0 to 1 during the evaluation phase, the charge initially stored in C 1 will be shared by C 2. Therefore, the value of VX will reduced. 47 CMOS Digital Integrated Circuits

Domino CMOS Logic Reduce Charge Sharing Degradation of VX VDD weak pull-up p. MOS VX inputs 48 n. MOS Logic Vout Push VX to VDD unless there is a strong pull-down path between Vout and ground CMOS Digital Integrated Circuits

Domino CMOS Logic Reduce Charge Sharing Degradation of VX (Cont. ) VDD • VX 1 n. MOS Logic Vout 1 C 1 Vout 2 • VX 2 n. MOS Logic • C 2 • Use separate p. MOS transistors to precharge all intermediate nodes in n. MOS pull-down tree which have a large parasitic capacitance. Effectively eliminate all charge sharing problems during evaluation Allow implementation of multipleoutput domino structures. Can cause additional delay since the n. MOS tree need to drain a larger charge to pull down VX Another Way: Use a smaller threshold voltage the final stage output is not affected by lowering of VX trade off the pull-up speed (weaker p. MOS transistor) 49 CMOS Digital Integrated Circuits

Domino CMOS Logic An Example of Using Separate p. MOS Transistor VDD VDD VX 1 VA VB 50 VX 2 C 2 Vout C 1 • Let C 1 = C 2 = 0. 05 p. F. VX 1 = 0, and VX 2 = 0 at t=0 • Without this extra p. MOS transistor » Precharge: VX 1 ≠VX 2 » Evaluation: VX 1 = VDDC 1/(C 1+C 2) = VDD/2 • With this extra p. MOS transistor » Presharge: VX 1 = VX 2 » Evaluation: VX 1 = VDD • See pp. 392~393 for the HSPICE simulation result • Note that there is a speed penalty for adding this extra p. MOS precharge transistor. CMOS Digital Integrated Circuits

Domino CMOS Logic An Example of Multiple-Output Domino Circuits VDD C 4 P 3 P 2 P 1 G 4 C 3 G 3 C 2 G 2 C 1 G 1 C 0 Reduce transistor count • • 51 C 1=G 1+P 1 C 0 C 2=G 2+P 2 G 1+P 2 P 1 C 0 C 3=G 3+P 3 G 2+P 3 P 2 G 1+P 3 P 2 P 1 C 0 C 4=G 4+P 4 G 3+P 4 P 3 G 2+P 4 P 3 P 2 G 1+P 4 P 3 P 2 P 1 C 0 Gi = A i · B i Pi = A i Bi CMOS Digital Integrated Circuits

FET Scaling in Domino CMOS Gates n The transient performance can be improved by adjusting the n. MOS transistor sizes in the pull-down path to reduce the discharge time. VDD D Mp C B A Vout CL A B C R 0 D Me 52 R 1 1 0 C 1 CL CMOS Digital Integrated Circuits

The n. MOS Scaling in Domino CMOS Gates R 0 n n n n 53 0 R 1 1 V 1=V 0=VDD VDDe-1 after time T 1 C 0 C 1 CL T 1 =R 0(C 0+C 1+CL)+R 1(C 1+CL) Let the last n. MOS is increased by a fraction of ∆k then C 1(1+∆k); R 1/(1+∆k) T 1 =R 0(C 0+C 1+CL)+R 1(C 1+CL)+(C 1 -R 1 CL/R 0)∆k If CL<(R 0/R 1)C 1 T 1 decreases by decreasing the size of the last n. MOS. R 0/R 1 is the number of series-connected n. MOS minus one, times a factor γ that takes the many effects that makes a real n. MOS different from a linear resistor, into account. Using the approximation γ=1/2, we conclude If CL<C 1(N-1)/2 is satisfied, the overall delay can be reduced by decreasing the size of last n. MOS. The above result can be iteratively applied to the other transistors, which leads to graded sizing of all n. MOS devices. CMOS Digital Integrated Circuits

NORA CMOS Logic (NP-Domino Logic) VDD n. MOS Logic p. MOS Logic to n. MOS stage precharge p. MOS stage pre-discharge VDD all stages evaluate to p. MOS stage n. MOS stage precharge p. MOS stage pre-discharge all stages evaluate • Advantages » An Inverter is not required at the output of stages » Allow pipelined system architecture • Disadvantages: Also suffer from charge sharing and leakage 54 CMOS Digital Integrated Circuits

NORA CMOS Logic (NP-Domino Logic) Examples VDD VDD • =L: n. MOS precharges to H, and p. MOS pre-discharges to L. • =L→H: All cascaded n. MOS and p. MOS logic stages evaluate one after the other. 55 CMOS Digital Integrated Circuits

NORA CMOS Logic (NP-Domino Logic) Examples (Cont. ) • Pipelined System Architecture: See Fig. 9. 39 – Use of CMOS 2 latches (three state latches storing on logic inputs. ) • Zipper Logic: See Fig. 9. 40 – Identical to NORA except for weird clock signals that keep precharge devices weakly on to handle charge leakage and charge sharing 56 CMOS Digital Integrated Circuits

Pipelined True Single-Phase Clock (TSPC) Dynamic CMOS VDD VDD n. MOS Logic N-block p. MOS Logic to next N-block P-block Using tristate inverters between stages decouples the stages and enables pipelined operation • =L: n. MOS blocks precharge to VDD p. MOS blocks evaluate by selective pull-up to VDD • =H: p. MOS blocks pre-discharge to VDD n. MOS blocks evaluate by selective pull-down to 0 V • is not used, no clock skew problem can arise. • Provide similar performance to NORA structure 57 CMOS Digital Integrated Circuits

TSPC-Based Rising Edge-triggered D-type Flip-Flop VDD D VDD VDD Q • Need only 11 transistors. • Static Edge Triggered D Flip-flop (see Fig. 8. 30) need 16 transistors. n Common Advantages of dynamic Logic Styles • Smaller area than fully static gates. • higher speed: smaller parasitic capacitances. • Glitch free operation if design carefully 58 CMOS Digital Integrated Circuits

Summary • Full complementary static logic is best option in the majority of CMOS circuits. » Noise-immunity is not sensitive to kn/kp » Does not involve precharge of nodes » Dissipate no DC power » Layout can be automated » Large fan-in gates lead to complex circuit structures (2 N transistors) » Larger parasitics » Slower and higher dynamic power dissipation than alternatives » No clock 59 CMOS Digital Integrated Circuits

Summary (Cont. ) • Pseudo-n. MOS static logic finds widest utility in large fan-in NOR gates. » Require only N+1 transistors for N fan-in » Smaller parasitics » Faster and lower dynamic power dissipation than full CMOS » Noise immunity sensitive to kn/kp » Dissipate DC power when pulled down » Not well suited for automated layout » No clock 60 CMOS Digital Integrated Circuits

Summary (Cont. ) • CMOS domino logic should be used for low-power, high speed applications » Require only N+k transistors for N fan-in, size advantages of pseudo-n. MOS. » Dissipate no DC power » Noise immunity is not sensitive to kn/kp » Use of clocks enables synchronous operation » Rely on storage on soft node » Require exhaustive simulation at all the process corners to insure properation » Some of the speed advantage over static gates is diminished by the required per-charge (pre-discharge) time. 61 CMOS Digital Integrated Circuits