ESE 370 CircuitLevel Modeling Design and Optimization for

ESE 370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: September 27, 2013 Variation Penn ESE 370 Fall 2013 -- De. Hon 1

Previously • Understand how to model transistor behavior • Given that we know its parameters – Vdd, Vth, t. OX, COX, W, L, NA … CGCS CGCB Penn ESE 370 Fall 2013 -- De. Hon 2

But… • We don’t know its parameters (perfectly) 1. Fabrication parameters have error range 2. Identically drawn devices differ 3. Parameters change with environment (e. g. Temperature) 4. Parameters change with time (aging) Why I am more concerned with robustness than precision. Penn ESE 370 Fall 2013 -- De. Hon 3

Today • Sources of Variation – Fabrication – Operation – Aging • Coping with Variation – Margin – Corners – Binning Penn ESE 370 Fall 2013 -- De. Hon 4

Fabrication Penn ESE 370 Fall 2013 -- De. Hon 5

Variation Types • Many reasons why things are different – Show up in many different ways. • Scales – Wafer-to-wafer, die-to-die, transistor-totransistor • Correlations – Systematic, spatial, random (uncorrelated) Penn ESE 370 Fall 2013 -- De. Hon 6

Source: Noel Menezes, Intel ISPD 2007 Penn ESE 370 Fall 2013 -- De. Hon 7

Process Shift • • Oxide thickness Doping level Layer alignment Growth and Etch rates and times – Depend on chemical concentrations • How precisely can we control those? • Vary machine-to-machine, day-to-day • Impact all transistors on wafer Penn ESE 370 Fall 2013 -- De. Hon 8

Systematic Spatial • Parameters change consistently across wafer or chip based on location • Chemical-Mechanical Polishing (CMP) – Dishing • Lens distortion Penn ESE 370 Fall 2013 -- De. Hon 9

FPGA Systematic Variation • 65 nm • Virtex 5 Penn ESE 370 Fall 2013 -- De. Hon [Tuan et al. / ISQED 2010] 10

Oxide Thickness [Asenov et al. TRED 2002] Penn ESE 370 Fall 2013 -- De. Hon 11

Line Edge Roughness • 1. 2 mm and 2. 4 mm lines From: http: //www. microtechweb. com/2 d/lw_pict. htm Penn ESE 370 Fall 2013 -- De. Hon 12

Optical Sources • What is the shortest wavelength of visible light? • How compare to 45 nm feature size? Penn ESE 370 Fall 2013 -- De. Hon 13

Phase Shift Masking Today’s chips use λ=193 nm Source http: //www. synopsys. com/Tools/Manufacturing/Mask. Synthesis/PSMCreate/Pages/default. aspx Penn ESE 370 Fall 2013 -- De. Hon 14

Line Edges (PSM) Source: http: //www. solid-state. com/display_article/122066/5/none/Feat/Developments-in-materials-for-157 nm-photoresists Penn ESE 370 Fall 2013 -- De. Hon 15

Intel 65 nm SRAM (PSM) Source: http: //www. intel. com/technology/itj/2008/v 12 i 2/5 -design/figures/Figure_5_lg. gif 16 Penn ESE 370 Fall 2013 -- De. Hon

Statistical Dopant Placement Penn ESE 370 Fall 2013 -- De. Hon 17 [Bernstein et al, IBM JRD 2006]

Random Trans-to-Trans • • Random dopant fluctuation Local oxide variation Line edge roughness Etch and growth rates – Stochastic process • Transistors differ from each other in random ways Penn ESE 370 Fall 2013 -- De. Hon 18

Source: Noel Menezes, Intel ISPD 2007 Penn ESE 370 Fall 2013 -- De. Hon 19

Impact • Changes parameters – W, L, t. OX, Vth • Change transistor behavior – W? – L? – t. OX? Penn ESE 370 Fall 2013 -- De. Hon 20

Example: Vth • Many physical effects impact Vth – Doping, dimensions, roughness • Behavior highly dependent on Vth Penn ESE 370 Fall 2013 -- De. Hon 21

Vth Variability @ 65 nm Penn ESE 370 Fall 2013 -- De. Hon 22 [Bernstein et al, IBM JRD 2006]

Impact of Vth Variation? • Higher VTH? – Not drive as strongly – Id, vsat (Vgs-VTH) – Performance? Penn ESE 370 Fall 2013 -- De. Hon 23

Impact Performance • Vth Ids Delay (Ron * Cload) Penn ESE 370 Fall 2013 -- De. Hon 24

Impact of Vth Variation Penn ESE 370 Fall 2013 -- De. Hon Think NMOS Vgs = Vdd 25

FPGA Logic Variation • Xilinx Virtex 5 • 65 nm • Altera Cyclone-II • 90 nm [Tuan et al. / ISQED 2010] Penn ESE 370 Fall 2013 -- De. Hon [Wong, FPT 2007] 26

Variation in 65 nm FPGAs [Gojman, FPGA 2013] De. Hon May 2013 27

LUT-to-LUT Same LAB • LAB (27, 22) [Gojman, FPGA 2013] De. Hon May 2013 average 5% variation 28

Delay Map • LAB (27, 22) [Gojman, FPGA 2013] De. Hon May 2013 29

Two LUT 2 LUT across Chip De. Hon May 2013 30

Reduce Vdd (Cyclone IV 60 nm LP) [Gojman, FPGA 2013] De. Hon May 2013 31

Impact of Vth Variation? • Lower VTH? – Not turn off as well leaks more Penn ESE 370 Fall 2013 -- De. Hon 32

2004 Borkar (Intel) Micro 37 (2004) Penn ESE 370 Fall 2013 -- De. Hon 33

Operation Temperature Voltage Penn ESE 370 Fall 2013 -- De. Hon 34

Temperature Changes • Different ambient environments – January in Maine – July in Philly – Air conditioned machine room • Self heat from activity of chip • Quality of heat sink (attachment thereof) Penn ESE 370 Fall 2013 -- De. Hon 35

Self Heating Borkar (Intel) Micro 37 (2004) Penn ESE 370 Fall 2013 -- De. Hon 36

Thermal Profile for Processor Penn ESE 370 Fall 2013 -- De. Hon 37 [Reda/IEEE Tr Emerging CAS v 1 n 2 2011]

How does temperature impact on-current? • High temperature – More free thermal energy • Easier to conduct • Lowers Vth – Increase rate of collision • Lower saturation velocity • Lower saturation voltage • Lower peak Ids slows down • One reason don’t want chips to run hot Penn ESE 370 Fall 2013 -- De. Hon 38

Temperature and Ids Penn ESE 370 Fall 2013 -- De. Hon 39

How does temperature impact leakage current? • High temperature Lowers Vth Penn ESE 370 Fall 2013 -- De. Hon 40

Voltage • Power supply isn’t perfect • Differs from design to design – Board to board? – How precise is regulator? • IR-drop in distribution • Bounce with current spikes Penn ESE 370 Fall 2013 -- De. Hon 41

Aging Hot Carrier NBTI Penn ESE 370 Fall 2013 -- De. Hon 42

Hot Carriers • Trap electrons in oxide – Also shifts Vth Penn ESE 370 Fall 2013 -- De. Hon 43

NBTI • Negative Bias Temperature Instability – Interface traps, Holes • Long-term negative gate-source voltage – Affects PFET most • Increase Vth • Partially recoverable? • Temperature dependent Another reason not to run hot. Penn ESE 370 Fall 2013 -- De. Hon [Stott, FPGA 2010] 44

Measured Accelerated Aging (Cyclone III, 65 nm FPGA) Penn ESE 370 Fall 2013 -- De. Hon [Stott, FPGA 2010] 45

Coping with Variation Penn ESE 370 Fall 2013 -- De. Hon 46

Variation • See a range of parameters – L: Lmin – Lmax – Vth: Vth, min – Vth, max Penn ESE 370 Fall 2013 -- De. Hon 47

Impact of Vth Variation • Higher VTH – Not drive as strongly – Id, vsat (Vgs-VTH) • Lower VTH – Not turn off as well leaks more Penn ESE 370 Fall 2013 -- De. Hon 48

Variation • Margin for expected variation • Must assume Vth can be any value in range – Speed assume Vth slowest value Ion, min=Ion(Vth, max) Probability Distribution Id, vsat (Vgs-Vth) VTH Penn ESE 370 Fall 2013 -- De. Hon 49

Gaussian Distribution From: http: //en. wikipedia. org/wiki/File: Standard_deviation_diagram. svg 50 Penn ESE 370 Fall 2013 -- De. Hon

Impact • Given – Vth, nom = 250 m. V – Sigma 25 m. V • Probability of 100 transistor circuit in range when each has 96% prob. ? • …when each has 99. 8% probability? Penn ESE 370 Fall 2013 -- De. Hon 51

Impact • Given – Vth, nom = 250 m. V – Sigma 25 m. V • What maximum Vth should expect to see for a circuit of – 100 transistors? – 109 transistors? Penn ESE 370 Fall 2013 -- De. Hon 52

Variation • See a range of parameters – L: Lmin – Lmax – Vth: Vth, min – Vth, max • Validate design at extremes – Work for both Vth, min and Vth, max ? – Design for worst-case scenario Penn ESE 370 Fall 2013 -- De. Hon 53

Margining • Also margin for – Temperature – Voltage – Aging: end-of-life Penn ESE 370 Fall 2013 -- De. Hon 54

Process Corners • Many effects independent • Many parameters • With N parameters, – Look only at extreme ends (low, high) – How many cases? • Try to identify the {worst, best} set of parameters – Slow corner of design space, fast corner • Use corners to bracket behavior Penn ESE 370 Fall 2013 -- De. Hon 55

Simple Corner Example What happens at various corners? 350 m. V Vthp 150 m. V 350 m. V Vthn Penn ESE 370 Fall 2013 -- De. Hon 56

Process Corners • Many effects independent • Many parameters • Try to identify the {worst, best} set of parameters – E. g. Lump together things that make slow • Vthn, Vthp, temperature, Voltage • Try to reduce number of unique corners – Slow corner of design space • Use corners to bracket behavior Penn ESE 370 Fall 2013 -- De. Hon 57

Range of Behavior Probability Distribution • Still get range of performances • Any way to exploit the fact some are faster? Delay Penn ESE 370 Fall 2013 -- De. Hon 58

Probability Distribution Speed Binning Sell Premium Sell nominal cheap Discard Delay Penn ESE 370 Fall 2013 -- De. Hon 59

Idea • Parameters Approximate • Differ – Chip-to-chip, transistor-to-transistor, over time • Robust design accommodates – Tolerance and Margins – Doesn’t depend on precise behavior Penn ESE 370 Fall 2013 -- De. Hon 60

Midterm 1 • Contents should not be a surprise – Identify CMOS/non-CMOS – Identify CMOS function – Any logic function CMOS gate – Noise Margins – Circuit quasistatic configuration and switching delay Penn ESE 370 Fall 2013 -- De. Hon 61

Admin • Midterm Monday – 7— 9 pm in Towne 309 • Previous midterm – Solutions linked to 2010 --2012 syllabus • But only one midterm in 2010 so parts more advanced than where we are now • Review on Sunday – 5: 30 pm Penn ESE 370 Fall 2013 -- De. Hon 62