ESE 370 CircuitLevel Modeling Design and Optimization for

ESE 370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 23: November 2, 2012 Pass Transistor Logic: part 2 (Cascading without Buffers) Penn ESE 370 Fall 2012 -- De. Hon 1

Previously Penn ESE 370 Fall 2012 -- De. Hon 2

Two XOR Gates Penn ESE 370 Fall 2012 -- De. Hon 3

Today • Pass Transistor Circuit – Output levels – Cascading • Series pass transistors? • Delay • Transmission gates • Tristate gates Penn ESE 370 Fall 2012 -- De. Hon 4

Cascading Pass Transistors Penn ESE 370 Fall 2012 -- De. Hon 5

Chain without Inverters • What if we did this? Penn ESE 370 Fall 2012 -- De. Hon 6

Extract key path Penn ESE 370 Fall 2012 -- De. Hon 7

t=0 (after Vin transition 1 0) Penn ESE 370 Fall 2012 -- De. Hon 8

t=4 t (after Vin transition 1 0) Penn ESE 370 Fall 2012 -- De. Hon 9

t=∞ (after Vin transition 1 0) Penn ESE 370 Fall 2012 -- De. Hon 10

Focus on Pass tr • Vgs? • Operation mode? • Current flow? Penn ESE 370 Fall 2012 -- De. Hon 11

Voltage of Chain • What is voltage at output? Penn ESE 370 Fall 2012 -- De. Hon 12

How compare • Compare Penn ESE 370 Fall 2012 -- De. Hon 13

DC Analysis Penn ESE 370 Fall 2012 -- De. Hon 14

DC Analysis – chain of 6 Penn ESE 370 Fall 2012 -- De. Hon 15

Conclude • Can chain any number of pass transistors and only drop a single Vth Penn ESE 370 Fall 2012 -- De. Hon 16

Transient Penn ESE 370 Fall 2012 -- De. Hon 17

Closeup Penn ESE 370 Fall 2012 -- De. Hon 18

Capacitance • What is Capacitance per stage (@y)? Penn ESE 370 Fall 2012 -- De. Hon 19

Delay • Delay as a function of chain length? Penn ESE 370 Fall 2012 -- De. Hon 20

Compare • CMOS • Buffered Pass TR • Unbuffered Pass TR • Delay • Area Penn ESE 370 Fall 2012 -- De. Hon 21

Pass TR Tree • What if we did this? Penn ESE 370 Fall 2012 -- De. Hon 22

Path • What’s different about this? Penn ESE 370 Fall 2012 -- De. Hon 23

Gate Cascade? • What are voltages? Penn ESE 370 Fall 2012 -- De. Hon 24

Demonstration Circuit Penn ESE 370 Fall 2012 -- De. Hon 25

SPICE • TODO show spice results of voltages Penn ESE 370 Fall 2012 -- De. Hon 26

Demonstration Chain Penn ESE 370 Fall 2012 -- De. Hon 27

Spice Penn ESE 370 Fall 2012 -- De. Hon 28

Conclude • Cannot cascade degraded inputs into gates. Penn ESE 370 Fall 2012 -- De. Hon 29

Midterm 2 Topics • Tau-model – Estimation and optimization • Elmore-delay – Estimation and optimization • Energy and power – Estimation and optimization – Dynamic and static • Logic – CMOS – Ratioed – Pass transistor • Scaling • Noise Margins • No clocking – Except to motivate delay targets and power calculations Note: 2010 midterm and 2011 midterm 2 Penn ESE 370 Fall 2012 -- De. Hon 30

Time Permitting… Penn ESE 370 Fall 2012 -- De. Hon 31

Other Gates Penn ESE 370 Fall 2012 -- De. Hon 32

Other gates • What does this do? B A More examples in book. Penn ESE 370 Fall 2012 -- De. Hon 33

Pass Rail-to-Rail Penn ESE 370 Fall 2012 -- De. Hon 34

Transmission Gate • Voltage levels at output? Penn ESE 370 Fall 2012 -- De. Hon 35

Bus Drivers Penn ESE 370 Fall 2012 -- De. Hon 36

Tristate Driver Penn ESE 370 Fall 2012 -- De. Hon 37

Tri-State Drivers Penn ESE 370 Fall 2012 -- De. Hon 38

Idea • There are other circuit disciplines • Can use pass transistors for logic – Even chains of pass transistors – Sometimes gives area or delay win • Do not cascade as easily as CMOS Penn ESE 370 Fall 2012 -- De. Hon 39

Admin • Project – Due Saturday • Daylight Savings Time change this weekend – …get an extra hour to study for… • Midterm 2: Nov. 7 th – Evening Wednesday Penn ESE 370 Fall 2012 -- De. Hon 40