ESE 370 CircuitLevel Modeling Design and Optimization for

ESE 370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 2: September 7, 2012 Transistor Introduction Penn ESE 370 Fall 2012 -- De. Hon 1

Today • MOSFET • Capacitive and resistive loads • Zero-th order transistor model – Good enough for [what? ] • Diagnostic Quiz (12: 40 pm) Penn ESE 370 Fall 2012 -- De. Hon 2

MOSFET • Metal Oxide Semiconductor Field Effect Transistor – New device – Primary active component for the term – Three terminal device • Voltage at gate controls conduction between two other terminals (source, drain) Penn ESE 370 Fall 2012 -- De. Hon 3

MOSFET Ids vs. Vgs, Vds Vgs = Vg-Vs Vds = Vd-Vs IDS Penn ESE 370 Fall 2012 -- De. Hon 4

MOSFET I vs. Vgs, Vds • Will dig into understanding during term • Today: simple ways to reason about gross behavior – Static/DC Penn ESE 370 Fall 2012 -- De. Hon 5

Preclass • What voltage do the cases converge to? Penn ESE 370 Fall 2012 -- De. Hon 6

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Conclude? • DC/Steady-State – Ignore the capacitors Penn ESE 370 Fall 2012 -- De. Hon 11

Quasistatic • Static – inputs (and circuit) unchanging, how does it settle? • Dynamic – what happens when things change • Quasi-Static – inputs transition, circuit responds, and settles – Dynamic transition to roughly static states Penn ESE 370 Fall 2012 -- De. Hon 12

Quasistatic Relevance? • How relevant to a combinational digital circuit? • How relevant to a clocked digital circuit? Penn ESE 370 Fall 2012 -- De. Hon 13

Zero-th Order MOSFET • Ideal Switch Vgs > Vth conducts Vgs < Vth does not conduct Vth – threshold voltage • Gate draws no current from input – Loads input capacitively Penn ESE 370 Fall 2012 -- De. Hon 14

Zero-th Order MOSFET IDS Vgs = Vg-Vs Penn ESE 370 Fall 2012 -- De. Hon 15

N-Type, P-Type MOSFET • N – negative carriers • P – positive carriers – electrons • Switch turned on positive Vgs – holes • Switch turned on negative Vgs Vthp<0 Vgs<Vthp to to conduct Penn ESE 370 Fall 2012 -- De. Hon 16

Symmetry • Device is symmetric • N-type: • Doesn’t know source – Electrons are carriers from drain – Electrons charged? • negative • Think of it as a – Electrons flow from resistor: – Also doesn’t know difference between two ends – Which way does current flow? Penn ESE 370 Fall 2012 -- De. Hon src drain – From which voltage? • Lowest voltage highest – Drain is ? • most positive terminal 17

Symmetry • Device is symmetric • Doesn’t know source • P-type: – Holes are carries from drain – Holes charged how? • Think of it as a • positively resistor: – Which way does current flow? – Holes flow from src drain – From which voltage? • Highest voltage lowest – Drain is? • most negative terminal Penn ESE 370 Fall 2012 -- De. Hon 18

Zero-th Order MOSFET IDS Penn ESE 370 Fall 2012 -- De. Hon 19

Why zero-order useful? Penn ESE 370 Fall 2012 -- De. Hon 20

What happens when Vin=Vdd>Vthn Penn ESE 370 Fall 2012 -- De. Hon Vgs = Vg-Vs Vthp=-Vthn 21

What happens when Vin=Vdd>Vth Penn ESE 370 Fall 2012 -- De. Hon Vgs=Vg-Vs=Vdd > Vthn Vthp=-Vthn 22

What happens when Vin=Vdd>Vth Penn ESE 370 Fall 2012 -- De. Hon Vgs=Vdd > Vthp=-Vthn 23

What happens when Vin=Vdd>Vth Vthp=-Vthn Vgs=0 > Vthp Penn ESE 370 Fall 2012 -- De. Hon Vgs=Vdd > Vth 24

What happens when Vin=Vdd>Vth Vthp=-Vthn Vgs=0 > Vthp Penn ESE 370 Fall 2012 -- De. Hon Vgs=Vdd > Vthn 25

What happens when Vin=Vdd>Vth Vthp=-Vthn Vgs=0 > Vthp V 2=Gnd Penn ESE 370 Fall 2012 -- De. Hon Vgs=Vdd > Vthn 26

What happens when Vin=Vdd>Vth Vthp=-Vthn Vgs=0 > Vthp V 2=Gnd Penn ESE 370 Fall 2012 -- De. Hon Vgs=Vdd > Vthn Vgs=0 < Vthn 27

What happens when Vin=Vdd>Vth Vgs=0 > Vthp=-Vthn Vgs=-Vdd < Vthp V 2=Gnd Penn ESE 370 Fall 2012 -- De. Hon Vgs=Vdd > Vthn Vgs=0 < Vthn 28

What happens when Vin=Vdd>Vth Vgs=0 > Vthp=-Vthn Vgs=-Vdd < Vthp V 2=Gnd Penn ESE 370 Fall 2012 -- De. Hon Vgs=Vdd > Vthn Vgs=0 < Vthn Vout=Vdd 29

What happens when Vin=0<Vth Penn ESE 370 Fall 2012 -- De. Hon Work on board 30

What happens when Vin=0<Vth V 2=Vdd Penn ESE 370 Fall 2012 -- De. Hon Vout=0 31

What function? Buffer • Vin=Vdd Vout=Vdd • Vin=0 Vout=0 Penn ESE 370 Fall 2012 -- De. Hon 32

Why Zeroth Order Useful? • Allows us to reason (mostly) at logic level about steady-state functionality of typical gate circuits • Make sure understand logical function (achieve logical function) before worrying about performance details Penn ESE 370 Fall 2012 -- De. Hon 33

Why adequate? • Static analysis – can ignore capacitors • Capacitive loads – resistances don’t matter • Feed forward for gates – – don’t generally have loops – can work forward from known values • Logic drive rail-to-rail – Don’t have to reason about intermediate voltage levels Penn ESE 370 Fall 2012 -- De. Hon 34

What not tell us? • Delay • Dynamics • Behavior if not – Capacitively loaded – Acyclic (if there are Loops) – Rail-to-rail drive Penn ESE 370 Fall 2012 -- De. Hon 35

Admin • HW 1 out – Can begin reasoning through pr 1 from today’s lecture – Gate design next week • One more piece of advice: Should be thinking about this course every day. Penn ESE 370 Fall 2012 -- De. Hon 36

Big Ideas • MOSFET Transistor as switch • Purpose-driven simplified modeling – Aid reasoning – Sanity check – Simplify design Penn ESE 370 Fall 2012 -- De. Hon 37

Diagnostic Quiz Turnin Quiz and feedback before leaving (do not turnin preclass keep that) Penn ESE 370 Fall 2012 -- De. Hon 38