ESE 370 CircuitLevel Modeling Design and Optimization for
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ESE 370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 29: November 11, 2013 Memory Core: Part 1 Penn ESE 370 Fall 2013 -- De. Hon 1
Today • 5 T SRAM – Writing – Charge sharing – Precharge • DRAM Penn ESE 370 Fall 2013 -- De. Hon 2
Memory Bank Penn ESE 370 Fall 2013 -- De. Hon 3
5 T SRAM Memory Bit Penn ESE 370 Fall 2012 -- De. Hon 4
Write (preclass 1) • Assuming properly select only one WL, what does write circuit look like? – What transistors are ON when writing a 0 over a cell that holds a 1? – Drive with inverter at BL • Width Wwrite 1 V – Voltage written? Penn ESE 370 Fall 2013 -- De. Hon 5
Write (preclass 1) • Assuming properly select only one WL, what does write circuit look like? – Voltage written? 1 V Penn ESE 370 Fall 2013 -- De. Hon 6
Write Conclude? • Writing into cell is a ratioed operation. Penn ESE 370 Fall 2013 -- De. Hon 7
Preclass 2 • Initially – A @ 1 V – B @ 0 V • Close switch • Voltage at A? Penn ESE 370 Fall 2013 -- De. Hon 8
Preclass 2 Initially – A @ 1 V – B @ 0 V • QA=1 V*C 1=C 1 Close switch • Qtot=Vfinal*(C 1+C 0) • Charge conservation – QA=Qtot • C 1=Vfinal*(C 1+C 0) Penn ESE 370 Fall 2013 -- De. Hon 9
Consider (preclass 3) • Read: What happens to voltage at A when WL turns from 0 1? – Assume Waccess large – Waccess >> Wpu=1 – BL initially 0 – A initially 1 Penn ESE 370 Fall 2013 -- De. Hon 10
Voltage After enable Word Line • • QBL = 0 QA = (1 V)(g(2+Waccess)C 0) CBL>>CA=(g(2+Waccess)C 0) After enable Waccess (Waccess large) – Total charge QBL +QA roughly unchanged – Distributed over larger capacitance~=CBL – VA=VBL~= CA/CBL Penn ESE 370 Fall 2013 -- De. Hon 11
Larger Resistance? • What happens if Waccess small? – Waccess < Wpu Penn ESE 370 Fall 2013 -- De. Hon 12
Larger Resistance? • What happens if Waccess small? – Waccess < Wpu • Takes time to move charge from A to BL • Moves more slowly than replished by pu Penn ESE 370 Fall 2013 -- De. Hon 13
Simulation: Waccess=100 Penn ESE 370 Fall 2013 -- De. Hon 14
Simulation Penn ESE 370 Fall 2013 -- De. Hon 15
Charge Sharing • Conclude: charge sharing can pull down voltage Penn ESE 370 Fall 2013 -- De. Hon 16
Consider • What happens to voltage at A when WL turns from 0 1? – Assume Waccess large Penn ESE 370 Fall 2013 -- De. Hon 17
Simulation Waccess=20 Penn ESE 370 Fall 2013 -- De. Hon 18
Simulation Waccess=4 Penn ESE 370 Fall 2013 -- De. Hon 19
Charge Sharing • Conclude: charge sharing can lead to read upset – Charge redistribution adequate to flip state of bit Penn ESE 370 Fall 2013 -- De. Hon 20
How might we avoid? Penn ESE 370 Fall 2013 -- De. Hon 21
Charge to middle Voltage • Charge bitlines to Vdd/2 before begin read operation • Now charge sharing doesn’t swing to opposite side of midpoint Penn ESE 370 Fall 2013 -- De. Hon 22
Pre-Charge • Use one phase of clock to charge a node to some initial value before operation Precharge Transistor Can be large Penn ESE 370 Fall 2013 -- De. Hon 23
Pre-Charge • Use one phase of clock to charge a node to some initial value before operation Precharge Transistor Can be large Penn ESE 370 Fall 2013 -- De. Hon 24
Simulation Waccess=20 Penn ESE 370 Fall 2013 -- De. Hon 25
Compare • Both Waccess=20; vary precharge Penn ESE 370 Fall 2013 -- De. Hon 26
5 T SRAM Questions? Penn ESE 370 Fall 2013 -- De. Hon 27
DRAM Penn ESE 370 Fall 2013 -- De. Hon 28
1 T 1 C DRAM • Simplest case – Memory is capacitor – Feature of DRAM process is ability to make large capacitor compactly Penn ESE 370 Fall 2013 -- De. Hon 29
1 T DRAM • What happens when read this cell? Cbit << Cbl Penn ESE 370 Fall 2013 -- De. Hon 30
1 T DRAM • On read, charge sharing – VBL = (Cbit/CBL)Vstore • Small swing on bit line – Must be able to detect – Means • want large Cbit • limit bits/bitline so VBL large enough • Cell always depleted on read – Must be rewritten Penn ESE 370 Fall 2013 -- De. Hon 31
Dynamic RAM • Takes sharing idea one step further • Share refresh/restoration logic as well • Only left with access transistor and capacitor Penn ESE 370 Fall 2013 -- De. Hon 32
3 T DRAM Penn ESE 370 Fall 2013 -- De. Hon 33
3 T DRAM • How does this work? – Write? – Read? Penn ESE 370 Fall 2013 -- De. Hon 34
3 T DRAM • Correct operation not sensitive to sizing • Does not deplete cell on read • No charge sharing with stored state • All NMOS (single well) • Prechage Read. Data • Must use Vdd+VTN on W to write full voltage Penn ESE 370 Fall 2013 -- De. Hon 35
Some Numbers (memory) • Register as stand-alone element (14 T) 4 Kl 2 • Static RAM cell (6 T) 1 Kl 2 – SRAM Memory (single ported) • Dynamic RAM cell (DRAM process) 100 l 2 • Dynamic RAM cell (SRAM process) 300 l 2 Penn ESE 370 Fall 2013 -- De. Hon 36
Idea • Memory can be compact • Rich design space • Demands careful sizing Penn ESE 370 Fall 2013 -- De. Hon 37
Admin • Midterm 2 solutions – Now updated with problem 2 pix • HW 7 due tomorrow • Project 2 out – Due 2 weeks from tomorrow • Tuesday before Thanksgiving Penn ESE 370 Fall 2013 -- De. Hon 38