Digital Design An Embedded Systems Approach Using Verilog

Digital Design: An Embedded Systems Approach Using Verilog Chapter 7 Processor Basics Portions of this work are from the book, Digital Design: An Embedded Systems Approach Using Verilog, by Peter J. Ashenden, published by Morgan Publishers, 2007 Elsevier Inc. All rights reserved. Digital. Kaufmann Design — Chapter. Copyright 7 — Processor Basics

Verilog Embedded Computers n A computer as part of a digital system n n Performs processing to implement or control the system’s function Components n n n Processor core Instruction and data memory Input, output, and input/output controllers n n Accelerators n n For interacting with the physical world High-performance circuit for specialized functions Interconnecting buses Digital Design — Chapter 7 — Processor Basics 2

Verilog Memory Organization n Von Neumann architecture n n Single memory for instructions and data Harvard architecture n n Separate instruction and data memories Most common in embedded systems Digital Design — Chapter 7 — Processor Basics 3

Verilog Bus Organization n n Single bus for low-cost low-performance systems Multiple buses for higher performance Digital Design — Chapter 7 — Processor Basics 4

Verilog Microprocessors n n n Single-chip processor in a package External connections to memory and I/O buses Most commonly seen in general purpose computers n E. g. , Intel Pentium family, Power. PC, … Digital Design — Chapter 7 — Processor Basics 5

Verilog Microcontrollers n Single chip combining n n Microcontroller families n n Same processor, varying memory and I/O 8 -bit microcontrollers n n n Processor A small amount of instruction/data memory I/O controllers Operate on 8 -bit data Low cost, low performance 16 -bit and 32 -bit microcontrollers n Higher performance Digital Design — Chapter 7 — Processor Basics 6

Verilog Processor Cores n n Processor as a component in an FPGA or ASIC In FPGA, can be a fixed-function block n n Or can be a soft core n n n E. g. , Power. PC cores in some Xilinx FPGAs Implemented using programmable resources E. g. , Xilinx Micro. Blaze, Altera Nios-II In ASIC, provided as an IP block n n E. g. , ARM, Power. PC, MIPS, Tensilica cores Can be customized for an application Digital Design — Chapter 7 — Processor Basics 7

Verilog Digital Signal Processors n DSPs are processors optimized for signal processing operations n n E. g. , audio, video, sensor data; wireless communication Often combined with a conventional core for processing other data n Heterogeneous multiprocessor Digital Design — Chapter 7 — Processor Basics 8

Verilog Instruction Sets n A processor executes a program n n Instruction set: the repertoire of available instructions n n A sequence of instructions, each performing a small step of a computation Different processor types have different instruction sets High-level languages: more abstract n n E. g. , C, C++, Ada, Java Translated to processor instructions by a compiler Digital Design — Chapter 7 — Processor Basics 9

Verilog Instruction Execution n Instructions are encoded in binary n n A processor executes a program by repeatedly n n Stored in the instruction memory Fetching the next instruction Decoding it to work out what to do Executing the operation Program counter (PC) n Register in the processor holding the address of the next instruction Digital Design — Chapter 7 — Processor Basics 10

Verilog Data and Endian-ness n n Instructions operate on data from the data memory Byte: 8 -bit data n n Data memory is usually byte addressed 16 -bit, 32 -bit, 64 -bit words of data Digital Design — Chapter 7 — Processor Basics 11

Verilog The Gumnut Core n A small 8 -bit soft core n n n Instruction set illustrates features typical of 8 bit cores and processors in general Programs written in assembly language n n n Can be used in FPGA designs Each processor instruction written explicitly Translated to binary representation by an assembler Resources available on companions web site Digital Design — Chapter 7 — Processor Basics 12

Verilog Gumnut Storage Digital Design — Chapter 7 — Processor Basics 13

Verilog Arithmetic Instructions n Operate on register data and put result in a register n n n Condition codes n n n add, addc, subc Can have immediate value operand Z: 1 if result is zero, 0 if result is non-zero C: carry out of add/addc, borrow out of sub/subc addc and subc include C bit in operation Digital Design — Chapter 7 — Processor Basics 14

Verilog Arithmetic Instructions n Examples n n add sub r 3, r 4, r 1 r 5, r 1, 2 r 4, 1 Evaluate 2 x + 1; x in r 3, result in r 4 n add r 4, r 3 r 4, 1 ; double x ; then add 1 Digital Design — Chapter 7 — Processor Basics 15

Verilog Logical Instructions n Operate on register data and put result in a register n n and, or, xor, mask (and not) Operate bitwise on 8 -bit operands Can have immediate value operand Condition codes n n Z: 1 if result is zero, 0 if result is non-zero C: always 0 Digital Design — Chapter 7 — Processor Basics 16

Verilog Logical Instructions n Examples n n and or xor r 3, r 4, r 5 r 1, 0 x 80 r 5, 0 x. FF ; set r 1(7) ; invert r 5 Set Z if least-significant 4 bits of r 2 are 0101 n and sub r 1, r 2, 0 x 0 F ; clear high bits r 0, r 1, 0 x 05 ; compare with 0101 Digital Design — Chapter 7 — Processor Basics 17

Verilog Shift Instructions n Logical shift/rotate register data and put result in a register n n n shl, shr, rol, ror Count specified as a literal operand Condition codes n n Z: 1 if result is zero, 0 if result is non-zero C: the value of the last bit shifted/rotated past the end of the byte Digital Design — Chapter 7 — Processor Basics 18

Verilog Shift Instructions n Examples n n n r 4, r 1, 3 r 2, 4 Multiply r 4 by 8, ignoring overflow n n shl ror shl r 4, 3 Multiply r 4 by 10, ignoring overflow n shl add r 1, r 4, 1 ; multiply by 2 r 4, 3 ; multiply by 8 r 4, r 1 Digital Design — Chapter 7 — Processor Basics 19

Verilog Memory Instructions n Transfer data between registers and data memory n n Load register from memory n n r 1, (r 2)+5 stm r 1, (r 4)-2 Use r 0 if base address is 0 n n ldm Store from register to memory n n Compute address by adding an offset to a base register value ldm r 3, 23 ldm r 3, (r 0)+23 Condition codes not affected Digital Design — Chapter 7 — Processor Basics 20

Verilog Memory Instructions n Increment a 16 -bit integer in memory n n Little-endian: address location ldm r 1, (r 2) add r 1, 1 stm r 1, (r 2) ldm r 1, (r 2)+1 addc r 1, 0 stm r 1, (r 2)+1 of lsb in r 2, msb in next ; increment lsb ; increment msb ; with carry Digital Design — Chapter 7 — Processor Basics 21

Verilog Input/Output Instructions n I/O controllers have registers that govern their operation n Input from I/O register n n n inp r 3, 157 inp r 3, (r 0)+157 Output to I/O register n n Each has an address, like data memory Gumnut has separate data and I/O address spaces out r 3, (r 7)+0 Condition codes not affected Further examples in Chapter 8 Digital Design — Chapter 7 — Processor Basics 22

Verilog Branch Instructions n Programs can evaluate conditions and take alternate courses of action n n Condition codes (Z, C) represent outcomes of arithmetic/logical/shift instructions Branch instructions examine Z or C n n n bz, bnz, bc, bnc Add a displacement to PC if condition is true Specifies how many instructions forward or backward to skip n Counting from instruction after branch Digital Design — Chapter 7 — Processor Basics 23

Verilog Branch Example n Elapsed seconds in location 100 n n Increment, ldm r 1, add r 1, sub r 0, bnz +1 add r 1, stm r 1, wrapping to 0 after 59 100 r 1, 1 r 1, 60 ; Z set if r 1 = 60 ; Skip to store if r 0, 0 ; Z is 0 100 Digital Design — Chapter 7 — Processor Basics 24

Verilog Jump Instruction n Unconditionally skips forward or backward to specified address n n Changes the PC to the address Example: if r 1 = 0, clear data location 100 to 0; otherwise clear location 200 to 0 n n Assume instructions start at address 10 10: sub r 0, r 1, 0 11: bnz +2 12: stm r 0, 100 13: jmp 15 14: stm r 0, 200 15: . . . Digital Design — Chapter 7 — Processor Basics 25

Verilog Subroutines n A sequence of instructions that perform some operation n n Can call them from different parts of a program using a jsb instruction Subroutine returns with a ret instruction Digital Design — Chapter 7 — Processor Basics 26

Verilog Subroutine Example n Subroutine to increment second count n n n Address of count in r 2 ldm r 1, (r 2) add r 1, 1 sub r 0, r 1, 60 bnz +1 add r 1, r 0, 0 stm r 1, (r 2) ret Call to increment locations 100 and 102 n add jsb r 2, r 0, 100 20 r 2, r 0, 102 20 Digital Design — Chapter 7 — Processor Basics 27

Verilog Return Address Stack n The jsb saves the return address for use by the ret n n But what if the subroutine includes a jsb? Gumnut core includes an 8 -entry pushdown stack of return addresses Digital Design — Chapter 7 — Processor Basics 28

Verilog Miscellaneous Instructions n Instructions supporting interrupts n n n See Chapter 8 reti Return from interrupt enai Enable interrupts disi Disable interrupts wait Wait for an interrupt stby Stand by in low power mode until an interrupt occurs Digital Design — Chapter 7 — Processor Basics 29

Verilog The Gumnut Assembler n Gasm: translates assembly programs n n n Generates memory images for program text (binary-coded instructions) and data See documentation on web site Write a program as a text file n n Instructions Directives Comments Use symbolic labels Digital Design — Chapter 7 — Processor Basics 30

Verilog Example Program ; Program to determine greater of value_1 and value_2 text org jmp ; Data memory layout data value_1: byte value_2: byte result: bss 0 x 000 main ; start here on reset 10 20 1 ; Main program text org main: ldm sub bc stm jmp value_2_greater: stm 0 x 010 r 1, value_1 r 2, value_2 r 0, r 1, r 2 value_2_greater r 1, result finish r 2, result finish: finish jmp ; load values ; compare values ; value_1 is greater ; value_2 is greater ; idle loop Digital Design — Chapter 7 — Processor Basics 31

Verilog Gumnut Instruction Encoding n Instructions are a form of information n n Can be encoded in binary Gumnut encoding n n 18 bits per instruction Divided into fields representing different aspects of the instruction n Opcodes and function codes Register numbers Addresses Digital Design — Chapter 7 — Processor Basics 32

Verilog Gumnut Instruction Encoding Digital Design — Chapter 7 — Processor Basics 33

Verilog Encoding Examples n Encoding for addc r 3, r 5, 24 n Arithmetic immediate, fn = 001 n n 05 D 18 Instruction encoded by 2 ECFC n Digital Design — Chapter 7 — Processor Basics bnc -4 34

Verilog Other Instruction Sets n 8 -bit cores and microcontrollers n n Xilinx Pico. Blaze: like Gumnut 8051, and numerous like it n n n Originated as 8 -bit microprocessors Instructions encoded as one or more bytes Instruction set is more complex and irregular Complex instruction set computer (CISC) C. f. Reduced instruction set computer (RISC) 16 -, 32 - and 64 -bit cores n n Mostly RISC E. g. , Power. PC, ARM, MIPS, Tensilica, … Digital Design — Chapter 7 — Processor Basics 35

Verilog Instruction and Data Memory n In embedded systems n n Instruction memory is usually ROM, flash, SRAM, or combination Data memory is usually SRAM n n DRAM if large capacity needed Processor/memory interfacing n Gluing the signals together Digital Design — Chapter 7 — Processor Basics 36

Verilog Example: Gumnut Memory Digital Design — Chapter 7 — Processor Basics 37

Verilog Example: Gumnut Memory always @(posedge clk) // Instruction memory if (inst_cyc_o && inst_stb_o) begin inst_dat_i <= inst_ROM[inst_adr_o[10: 0]]; inst_ack_i <= 1'b 1; end else inst_ack_i <= 1'b 0; Digital Design — Chapter 7 — Processor Basics 38

Verilog Example: Gumnut Memory always @(posedge clk) // Data memory if (data_cyc_o && data_stb_o) if (data_we_o) begin data_RAM[data_adr_o] <= data_dat_o; data_dat_i <= data_dat_o; data_ack_i <= 1'b 1; end else begin data_dat_i <= data_RAM[data_adr_o]; data_ack_i <= 1'b 1; end else data_ack_i <= 1'b 0; Digital Design — Chapter 7 — Processor Basics 39

Verilog Example: Microcontroller Memory Digital Design — Chapter 7 — Processor Basics 40

Verilog 32 -bit Memory n Four bytes per memory word n n n Partial-word read n n Little-endian: lsb at least address Big-endian: msb at least address Read all bytes, processor selects those needed Partial-word write n Use byte-enable signals Digital Design — Chapter 7 — Processor Basics 41

Verilog Example: Micro. Blaze Memory Digital Design — Chapter 7 — Processor Basics 42

Verilog Cache Memory n For high-performance processors n n n Memory access time is several clock cycles Performance bottleneck Cache memory n n n Small fast memory attached to a processor Stores most frequently accessed items, plus adjacent items Locality: those items are most likely to be accessed again soon Digital Design — Chapter 7 — Processor Basics 43

Verilog Cache Memory n Memory contents divided into fixedsized blocks (lines) n n Cache copies whole lines from memory When processor accesses an item n If item is in cache: hit - fast access n n Occurs most of the time If item is not in cache: miss n n n Line containing item is copied from memory Slower, but less frequent May need to replace a line already in cache Digital Design — Chapter 7 — Processor Basics 44

Verilog Fast Main Memory Access n Optimize memory for line access by cache n Wide memory n n Burst transfers n n Send starting address, then read successive locations Pipelining n n n Read a line in one access Overlapping stages of memory access E. g. , address transfer, memory operation, data transfer Double data rate (DDR), Quad data rate (QDR) n Transfer on both rising and falling clock edges Digital Design — Chapter 7 — Processor Basics 45

Verilog Summary n Embedded computer n n Microprocessors, microcontrollers, and processor cores Soft-core processors for ASIC/FPGA Processor instruction sets n n n Processor, memory, I/O controllers, buses Binary encoding for instructions Assembly language programs Memory interfacing Digital Design — Chapter 7 — Processor Basics 46