Advanced Embedded Systems Lecture 8 Interrupts in Embedded

Advanced Embedded Systems Lecture 8 Interrupts in Embedded Systems 1

Advanced Embedded Systems The interrupt system of the SAB 8 x. C 166 microcontroller n Is made by three parts: q The normal interrupt processing system n n n q q The CPU temporarily suspends the current program execution and branches to an interrupt service routine (ISR) in order to service an interrupt requesting device; The current program status, meaning IP, PSW and CSP if segmentation mode is enabled, is saved on the internal stack; There are defined 16 priority levels; The Interrupt processing via the Peripheral Event Controller (PEC) system and The Trap system: n n Trap functions are activated in response to the execution of certain instructions; A trap can also be caused externally by the NON-Maskable Interrupt pin /NMI; Several hardware trap functions are provided and also a software trap function which is invoked by the TRAP instruction; The current program status is saved on the system stack; 2

Advanced Embedded Systems n The Interrupt processing via the Peripheral Event Controller (PEC) system q q n Is a faster mechanism for servicing any interrupt requesting source; The PEC performs a single byte or word transfer between any two memory locations from segment 0; the transfer is done through one of the 8 PEC Service Channels; During a PEC transfer, the normal program execution of the CPU is halted for 1 instruction cycle; there is no internal saving of the program status; PEC system uses the same prioritization scheme as the normal system; PEC requests have the higher priority; Interrupt system structure q q Each source of interrupt or PEC request have a separate interrupt control register and interrupt vector; The control register contains the interrupt request flag, the interrupt enable bit and the interrupt priority of the correspondent source; 3

Advanced Embedded Systems q q q q Each source request is activated by a specific event; The interrupt system is a vectored one; the vector table is situated in the lowest address zone of the segment 0; Each entry in the table may be programmed with the starting address of the ISR of the request corresponding to that entry; An entry is 4 bytes long except for the reset and the hardware trap vectors where the entry is 8 or 16 bytes; Each entry is allocated to a request by the hardware; this helps to rapidly identify the source that caused the request; Special cases represent the Reset and Trap vectors; class B hardware traps share the same vector entry and they are separated through the status flags from the Trap Flag Register, TFR; Reset sources have the highest priority; after any Reset, program execution starts from location 0000; For the special software TRAP instructions, the vector address is specified by the operand field of the instruction; 4

Advanced Embedded Systems 5

Advanced Embedded Systems n Normal interrupt processing and PEC service q q n Interrupt system registers q q q n The priority of service for interrupts and PEC requests is completely programmable; In each instruction cycle the CPU arbitrates between the requesting sources; the one with the higher priority will win and it will be serviced if its priority is higher than the current CPU priority in the PSW; The interrupt system is controlled globally by the PSW through a general interrupt enable bit, IEN and the CPU priority field, ILVL; The interrupt sources are controlled individually by their specific interrupt control registers; For PEC service, one additional dedicated register and 2 pointers must be programmed; Interrupt control registers q q An ICR is 8 bits wide and contains the complete interrupt status of the associated source; All ICRs are bit addressable and all bits can be read or written by software; 6

Advanced Embedded Systems n The figure shows the ICR for source xx: 7

Advanced Embedded Systems n xx. IR – Interrupt Request Flag q q n xx. IE – Interrupt Request Flag q n Is set by hardware whenever a service request from source xx occurs; Is automatically cleared upon entry to the interrupt service routine or upon service of the request by the PEC; In the case of PEC service, the Interrupt Request flag remains set if the COUNT field of the selected PEC channel goes to 0; this allows a normal CPU interrupt to respond to a completed PEC block transfer; Modifying the Interrupt Request flag by software causes the same effect as if it had been set or cleared by hardware; Enables or disables the acceptance of a service request; ILVL – Interrupt Priority Level Field q q q Specifies the priority level of a service request, values 0 – Fh; Interrupt requests that are programmed to priority levels 15 or 14, ILVL = 111 Xb, are serviced by the PEC, unless the COUNT field of the associated PEC channel contains zero; in this case, the request is normally serviced; Requests with levels 1 – 13 are normally serviced; 8

Advanced Embedded Systems q q q For interrupt requests which are selected for PEC service, the LSB of ILVL represents the MSB of the associated PEC channel number; that is, by programming a source on priority level 15, ILVL = 1111 b, PEC channels 7 – 4 can be selected and by programming it on level 14, ILVL = 1110 b, PEC channels 3 – 0 can be selected; the actual PEC channel number is then determined by the Group Priority Field, GLVL; During the prioritization process, the ILVL fields of all interrupt requesting sources are compared to the current CPU priority level, held in the ILVL field of PSW; An interrupt request of higher priority than the current CPU priority can interrupt the executing routine; An interrupt source programmed to priority level 0 will never be serviced by the CPU, because its priority level can never be higher than the CPU priority; Upon entry into an ISR, the priority level of the winning source is copied into the ILVL field of the PSW after saving the old PSW in the stack; Nesting of 15 ISRs of different priority levels is allowed; 9

Advanced Embedded Systems n GLVL – Interrupt Group Priority Field q q q The 2 bits mean the relative priority of an interrupt service request within a group of simultaneous requests on the same priority level; For sources which will be serviced by PEC, the 2 bits of GLVL represent the 2 LSBs of the associated PEC channel number; The group priority field is particularly relevant for resolving simultaneous interrupt requests from several sources having the same priority level; a tree type priority system is implemented; Up to 4 sources can be programmed to the same priority level; they are prioritized according to their group priority, where 3 is highest group priority and 0 is the lowest; This also means that simultaneous requests for PEC service are prioritized according to their PEC channel number, the PEC channel with the highest number having the highest priority; All interrupt sources that are enabled and programmed to the same priority level must always be programmed to different group priorities; otherwise, an incorrect interrupt vector will be generated; 10

Advanced Embedded Systems 11

Advanced Embedded Systems n PEC Service Channels Register Description q q n The PEC system has 8 PEC Service Channels; Each channel consists of a dedicated PEC Channel Counter/Control register and a pair for source and destination of the data transfer; PEC Channel Counter/Control Registers q q PECCy, y = 0 – 7; Each register specifies the task which is to be performed by the associated PEC channel; A specific PEC channel is selected by an interrupt source through the ILVL and GLVL fields in the ICR of the respective source; Next table shows all the PECCy registers: 12

Advanced Embedded Systems 13

Advanced Embedded Systems n INC – Interrupt Control Field q q n n Specifies whether the Source Pointer or the Destination Pointer of the associated PEC channel shall be incremented after a PEC data transfer; If INC = 00, the transfer will be performed between the same two memory locations; BWT – Byte/Word Transfer Selection Bit COUNT – PEC Transfer Counter Field q q Specifies the number of data transfers to be performed by the respective PEC Channel; If the value is 2 – FEh, it is decremented after each PEC data transfer; the xx. IE of the source that generated the PEC service request is reset; If the value is 1, it is decremented but xx. IE remains set; If the value is 0, no PEC data transfer will be performed; instead, a CPU interrupt request is generated on the same priority level as the original PEC request; the CPU will branch to the ISR of the source that generated the request; it can be used to reprogram the associated PEC service channel; 14

Advanced Embedded Systems q n If the value is FFh, the continuous transfer mode is selected for the respective PEC channel; it will not be decremented an unlimited number of transfers will be performed; this operation can be terminated only by disabling PEC service or by reprogramming its PEC Channel Counter/Control register; PEC Source and Destination Pointers q q Each PEC channel has allocated a Source Pointer, referred as SRCPx and a Destination Pointer, referred as DSTPx, x = 0 – 7; The addresses contained in the pointers are interpreted as direct 16 bit memory addresses in segment 0, so that data transfers can be performed between any two memory locations within the first 4 data pages; If word data transfer is selected for a specific PEC channel, i. e. bit BWT = 0, the respective pointers must contain a valid word address which points to an even byte boundary; otherwise the Illegal Word Access trap will be invoked when this channel is used; The pointers share the top 16 word locations of the internal RAM; if no PEC service is required for a specific PEC channel, the locations of the correspondent pointers can be used for general operations; 15

Advanced Embedded Systems 16

Advanced Embedded Systems n Interrupt processing via the PEC q q PEC mechanism is useful in many applications when fast data transfers must be performed, e. g. storing results from an A/D converter, transferring data with a serial channel and so on; The PEC data transfer does not affect the IP or the flags in the PSW, therefore no savings take place; this improves the overall system throughput and speeds up the servicing of peripheral requests; The PEC service have priority over requests for CPU interrupt service; exceptions are when CPU is executing a routine on priority levels 15 or 14; if the CPU executes a routine on CPU priority level 14, only PEC channels 4 – 7 can be used; if CPU executes on level 15, no PEC channel can be used; If an interrupt request is serviced by PEC, a byte or word data transfer takes place; after the transfer one of the 2 pointers can optionally be incremented and the COUNT field is decremented; when COUNT reaches 0, a normal CPU interrupt request is generated and the associated ISR can be used to reprogram the affected PEC channel; 17

Advanced Embedded Systems 18

Advanced Embedded Systems n Priority level structure q q q q All the requests for normal or PEC interrupts have programmable priorities; sources that have the same priority must receive different group priorities; The advantage is that the order of servicing simultaneous requests from different sources on the same priority level is not fixed; The source with the higher priority level and the highest group priority wins in the arbitration process; Up to 15 ISRs on different priority levels can be nested; The 2 highest priority levels are used by PEC requests; those levels can be used for high priority CPU interrupts if the COUNT field is 0; More flexibility can be added by modifying the ILVL field from the PSW; Next, an example of organization of several interrupt requests is presented; the 8 interrupts from class A have higher priority from those from class B and from those from class C; a prioritization exists also inside the requests from the same class; for example, the request form class A with ILVL = Ch and GLVL = 3 h has the highest priority; 19

Advanced Embedded Systems 20

Advanced Embedded Systems n Interrupt procedure q q If an interrupt request has been accepted, the current state of the machine is saved on the stack; PSW and IP are saved if segmentation is disabled and PSW, CSP and IP are saved if segmentation is enabled; The ISR must be terminated with a RETI instruction which will pop the saved information in reverse order; When entering in an ISR, a new context of the machine must be loaded; the fastest way is with a context switch which enables another set of GPRs; The context switch is done by executing the instruction SCXT CP, # new_value within the ISR before any GPR is accessed; the same instruction must be executed, of course with a different operand, before executing the RETI instruction; 21

Advanced Embedded Systems n External interrupts q q q External interrupts requests can use 19 port pins; For each of these pins, either a positive, a negative, or both a positive and a negative external transition can be selected to generate a request; the edge selection is done through the control register; In order to use any of the 19 pins, the correspondent direction control bit must be 0; 22

Advanced Embedded Systems n Trap functions q q q n Software traps q q q n Hardware and software traps; Trap functions are not maskable and always have priority over any other interrupt request; Trap functions can be used when immediate system reaction is required; The TRAP instruction causes a software call to an ISR; A trap number, specified as an operand of the instruction, determines which vector location will be used; The execution of a TRAP instruction has the same effect as if an interrupt at the same vector had occurred; Hardware traps q q Are used to identify faults or specific system states at runtime which cannot be identified at assembly time; There are 8 hardware trap functions; they are divided in class A and B; they have the highest priority; 23

Advanced Embedded Systems q q The traps of class A are: the external Non-Maskable Interrupt, the Stack Overflow and the Stack Underflow; they have the same priority but different vector addresses; The traps of class B are: Undefined Code, Protection fault, Illegal Word Operand Access and Illegal External Bus Access; they have the same priority and vector address; The Trap Flag Register, TFR, shows the source of a trap request by setting flags when the event occurs; the flags must be reset by software in the trap service routine; After the reset functions, which have the highest priority, the traps of class A have the second highest priority and the traps of class B follow; q A class A trap can interrupt a class B trap, but not other class A trap; q An internal hardware prioritization exists among the traps of class A; q The prioritization among several active class B traps is done by software in the trap service routine; 24

Advanced Embedded Systems 25

Advanced Embedded Systems The interrupt system of the MC 68332 microcontroller n n n n The CPU processes interrupts as a type of asynchronous exception; An exception is an event that preempts normal processing; Each exception has an allocated vector in an exception vector table that points to an associated ISR; After RESET, the table is located from the address $000000; this value can be changed through the Vector Base Register (VBR); it can be dynamically relocated for each task executed by an OS; The vector table is 1024 bytes long, meaning 256 exception vectors; 64 vectors are defined by the processor and 192 vectors are reserved for user definition as interrupt vectors; Except the RESET exception, all other exceptions have one long word entry in the table; the RESET has a 2 long words entry; A vector is an 8 bit number; it is obtained from the source of the exception that is an external device or the processor; 26

Advanced Embedded Systems 27

Advanced Embedded Systems n n An exception can be caused by internal or external events; Sources for internal exceptions are: q q n n Instructions: TRAP, TRAPcc, TRAPV, BKPT, CHK 2, RTE; Errors: illegal instructions, instruction fetches from odd addresses, word or long word operand accesses from odd addresses, privilege violations; Sources for external exceptions are: interrupts, breakpoints, bus errors, reset; Exception processing sequence (except RESET): q q The processor makes an internal copy of the status register; after that, the processor state bits in the status register are changed: S = 1, T 1 = T 0 = 0; for reset and interrupts, the interrupt priority mask is updated; The exception vector is obtained; Current processor status is saved; copies of the status register and program counter are loaded in a new created exception stack; The entry of the vector table is accessed and the content is loaded into the program counter; the execution at the new address starts; 28

Advanced Embedded Systems n n n The CPU can handle 7 interrupt request signals, /IRQ 7 – 1, each of them corresponding to an interrupt priority: /IRQ 1 has the lowest priority and /IRQ 7 has the highest priority; Interrupt recognition is determined by interrupt priority level and interrupt priority (IP) mask value; The interrupt priority mask consists of 3 bits in the CPU status register; binary values %000 - %111 provide 8 priority masks; Masks provide interrupt requests of a priority less than or equal to the mask value from being recognized and processed; /IRQ 7, however, is always recognized being a non maskable interrupt; Interrupt requests are sampled on consecutive falling edges of the system clock; to be valid, a request signal must be asserted for at least 2 consecutive clock periods; valid requests are processed at instruction boundaries or when exception processing of higher priority interrupts is complete; An active higher priority request is serviced while a lower one is pending; the interrupts request’s priority must be higher than the current IP mask; 29

Advanced Embedded Systems 30

Advanced Embedded Systems n Interrupt acknowledge and arbitration q q When the CPU detects one or more interrupt requests with a higher priority than the interrupt priority mask value, it places the interrupt request level on the address bus and initiates a CPU read cycle; The request level has 2 purposes: n n q q It is decoded by modules or external devices that have requested interrupt service, to determine whether the current interrupt acknowledge cycle pertains to them; It is latched in the CPU status register to preclude further interrupts of lower priority during interrupt service; Modules or external devices that have requested interrupt service must decode the IP mask value placed on the address bus during the interrupt acknowledge cycle and respond if the priority of the service request corresponds to the mask value; before that, the arbitration takes place; Arbitration is done by means of serial contention between values stored in individual module arbitration fields (IARB); each module that can make an interrupt service request has an IARB field in its configuration register; the values from IARB range from %0000 to %1111; 31

Advanced Embedded Systems q q q Each module that can request interrupt service must be assigned a unique, non-zero IARB field value during system initialization; arbitration priorities range between %0001 and %1111, the value %0000 leading to a spurious interrupt processing; Although arbitration is intended to deal with simultaneous requests of the same level, it always takes place, even when a single source is requesting service; When arbitration is complete, the module with both the highest asserted interrupt level and the highest priority arbitration priority must terminate the bus cycle: n n n Internal modules place an interrupt vector number on the data bus and generate appropriate internal cycle termination signals; External modules wait for the CPU to execute an interrupt acknowledge cycle and when it happens respond with a vector number, then generate data and size acknowledge, /DSACK, termination signals, or it must assert the autovector, /AVEC, request signal; If the device does not respond in time, the bus monitor from the CPU asserts the bus error signal, /BERR, and a spurious exception is considered; 32

Advanced Embedded Systems n Interrupt processing: q q q The CPU finishes higher priority exception processing or reaches an instruction boundary; The processor saves its state in a stack; the S bit is set, establishing supervisor access level and bits T 1 and T 0 are cleared disabling tracing; The interrupt acknowledge cycle begins: n n n q FC 2 – 0 are driven to %111, meaning a CPU space encoding; ADDR 23 – 20 = %1111, ADDR 19 – 16 = %1111, indicating that the cycle is an interrupt acknowledge CPU space cycle, ADDR 15 – 4 = %111111, ADDR 3 – 1 = the priority of the interrupt request being acknowledged and ADDR 0 = %1; The request level is latched from the address bus into the IP mask field in the status register; Modules that have requested interrupt service decode the priority value on ADDR 3 – 1; if request priority is the same as acknowledge priority, arbitration by IARB contention takes place; 33

Advanced Embedded Systems q After arbitration, the interrupt acknowledge cycle is completed in one of the following ways: n n q q When there is no contention, IARB = %0000, the spurious interrupt monitor asserts /BERR and the CPU generates the spurious interrupt vector number; The winning interrupt source supplies a vector number and /DSACK signals appropriate to the access; the CPU acquires the vector number; The /AVEC signal is asserted and the CPU generates the spurious interrupt vector number; the signal can be asserted by the winning external interrupt source or the pin can be tied low; The bus monitor asserts /BERR and the CPU generates the spurious interrupt vector number; The vector number is converted to a vector address; The content of the vector address is loaded into the PC and the ISR begins. 34