Interrupts Learning Objectives Introduction to interrupts Types of
Interrupts
Learning Objectives Introduction to interrupts. Types of interrupts and sources. Interrupt timeline. Handling and processing interrupts using C and assembly code. Chapter 10, Slide 2 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Introduction Interrupts are used to interrupt normal program flow, so that the CPU can respond to events like I/O demands An alternative to Interrupt is polling, where the program continuously tests whether data is available to be received or transmitted Chapter 10, Slide 3 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Introduction Servicing an interrupt involves saving the context of the current process, completing the interrupt task (interrupt service routine), restoring the process context, and resuming the original process. Chapter 10, Slide 4 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Introduction Chapter 10, Slide 5 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Interrupt Sources Types of interrupts on the ‘C 6000 CPUs Chapter 10, Slide 6 RESET NMI INT 4 INT 5 INT 6 INT 7 INT 8 INT 9 INT 10 INT 11 INT 12 INT 13 INT 14 INT 15 Highest priority Lowest priority Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Interrupt Sources The RESET signal resets the CPU and has the highest priority. NMI, the non-maskable interrupt, is the second–highest priority interrupt and is generally used to alert the CPU of a serious hardware problem such as an imminent power or memory failure [A non-maskable interrupt means that the interrupt cannot be ignored or disabled by the system]. INT 4 -INT 15 are maskable interrupts which means that the processor can mask or temporarily ignore the interrupt if it needs to, so it can finish something else that it is doing. These interrupts can be associated with external devices, on–chip peripherals, software control, or not be available. Chapter 10, Slide 7 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Interrupt Control Registers There are eight registers in the ‘C 6713 that control servicing interrupts. Interrupt Control Registers CSR (control status register): contains the global interrupt enable (GIE) bit and other control/status bits IER (interrupt enable register): enables/disables individual interrupts IFR (interrupt flag register): displays status of interrupts – if interrupt is pending ISR (interrupt set register): sets pending interrupts ICR (interrupt clear register): clears pending interrupts ISTP (interrupt service table pointer): locates an ISR IRP (interrupt return pointer) Chapter 10, Slide 8 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Generating a Maskable Interrupt An appropriate transition on an interrupt pin sets the pending status of the interrupt within the interrupt flag register (IFR). If the interrupt is properly enabled (conditions on next slide), the CPU begins processing the interrupt and redirecting program flow to the interrupt service routine. Chapter 10, Slide 9 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Generating a Maskable Interrupt The following conditions must be met to process a maskable interrupt: Chapter 10, Slide 10 The global interrupt enable bit (GIE) bit in the control status register (CSR) is set to 1 The NMIE bit in the interrupt enable register (IER) is set to 1 Corresponding interrupt enable (IE) bit in the IER is set to 1 The corresponding interrupt occurs, which sets the corresponding bit in the IFR to 1 and there are no higher priority interrupt flag (IF) bits set in the IFR. Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Generating a Maskable Interrupt The conditions for an interrupt to be handled: *GIE = 1 (not masking) *NMIE = 1 NMI enabled *IE for INT = 1 enabled No higher IFR = 1 Interrupt *Map Interrupt Transition IFR =1 Source 4 -15 for INT Chapter 10, Slide 11 x Process Interupt Process Interrupt Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Mapping Interrupt Sources to CPU Interrupts Sources (HPI) DSPINT TINT 0 TINT 1 SD_INT EXT_INT 4 EXT_INT 5 EXT_INT 6 EXT_INT 7 DMA_INT 0 DMA_INT 1 DMA_INT 2 DMA_INT 3 XINT 0 RINT 0 XINT 1 RINT 1 Description CPU Int High HPI Interrupt Timer 0 Timer 1 SDRAM Refresh External Interrupt 4 External Interrupt 5 External Interrupt 6 External Interrupt 7 DMA Channel 0 DMA Channel 1 DMA Channel 2 DMA Channel 3 Mc. BSP Channel 0 TX Mc. BSP Channel 0 RX Mc. BSP Channel 1 TX Mc. BSP Channel 1 RX RESET NMI reserved INT 4 INT 5 INT 6 INT 7 INT 8 INT 9 INT 10 INT 11 INT 12 INT 13 INT 14 INT 15 P r i o r i t y Low Note that there are more sources of interrupt than the CPU can handle. Chapter 10, Slide 12 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Interrupt Selection Sources (HPI) DSPINT TINT 0 TINT 1 SD_INT EXT_INT 4 EXT_INT 5 EXT_INT 6 EXT_INT 7 DMA_INT 0 DMA_INT 1 DMA_INT 2 DMA_INT 3 XINT 0 RINT 0 XINT 1 RINT 1 Description CPU Int High HPI Interrupt Timer 0 Timer 1 SDRAM Refresh External Interrupt 4 External Interrupt 5 External Interrupt 6 External Interrupt 7 DMA Channel 0 DMA Channel 1 DMA Channel 2 DMA Channel 3 Mc. BSP Channel 0 TX Mc. BSP Channel 0 RX Mc. BSP Channel 1 TX Mc. BSP Channel 1 RX RESET NMI reserved INT 4 INT 5 INT 6 INT 7 INT 8 INT 9 INT 10 INT 11 INT 12 INT 13 INT 14 INT 15 P r i o r i t y Low Each source interrupt can be made to trigger a specific CPU interrupt. Chapter 10, Slide 13 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Interrupt Selection The interrupt source mapping can be achieved by initializing the appropriate bit-fields of the interrupt multiplexer. Each CPU interrupt has a selection number “INTSEL#” that specifies the source. Interrupt Multiplexer High(INT 10 - INT 15) (address 0 x 19 c 0000) 29 26 INTSEL 15 24 21 INTSEL 14 19 16 INTSEL 13 13 10 INTSEL 12 8 5 INTSEL 11 3 0 INTSEL 10 Interrupt Multiplexer Low(INT 4 - INT 9) (address 0 x 19 c 0004) 29 26 INTSEL 9 Chapter 10, Slide 14 24 21 INTSEL 8 19 16 INTSEL 7 13 10 INTSEL 6 8 5 INTSEL 5 3 0 INTSEL 4 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Interrupt Selection Example: Mapping EXT_INT 5 to CPU INT 12. address 13 Write 5 dec = 0101 b to INTSEL 12 10 0101 0 x 19 c 0000 0 x 19 c 0004 Interrupt Multiplexer High(INT 10 - INT 15) (address 0 x 19 c 0000) 29 26 INTSEL 15 24 21 INTSEL 14 19 16 INTSEL 13 13 10 INTSEL 12 8 5 INTSEL 11 3 0 INTSEL 10 Interrupt Multiplexer Low(INT 4 - INT 9) (address 0 x 19 c 0004) 29 26 INTSEL 9 Chapter 10, Slide 15 24 21 INTSEL 8 19 16 INTSEL 7 13 10 INTSEL 6 8 5 INTSEL 5 3 0 INTSEL 4 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Interrupt Selection Writing code to initialize INT 12 with 0101 b, there are 3 methods: (1) Using assembly: MVKL 0 x 19 c 0000, A 1 MVKH 0 x 19 c 0000, A 1 LDW *A 1, A 0 CLR A 0, 13, A 0 SET A 0, 10, A 0 SET A 0, 12, A 0 STW A 0, *A 1 (2) Using the Chip Support Library (CSL): #include <intr. h> #include <regs. h> IRQ_map (IRQ_EVT_EXTINT 5, 12); Chapter 10, Slide 16 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Interrupt Selection (3) Using the GUI interface: Chapter 10, Slide 17 Open the CDB file. Select Hardware Interrupt Service Routine Manager. Select the CPU interrupt 12 (HWI_INT 12) and right click and select properties. Select External_Pin_5 as the interrupt source. Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Interrupt Processing User Responsibility (Initialization) Performed by the CPU User Responsibility (Algorithm) Chapter 10, Slide 18 Configure 1. Select interrupt sources and map them. 2. Create interrupt vector table. Enable 3. Enable individual interrupts. 4. Enable global interrupt. 5. 6. 7. Check for valid signal. Once a valid signal is detected set flag bit. Check if interrupt is enabled, if yes branch to ISR. 8. Write context store routine. 9. Write the ISR. 10. Write context restore routine. 11. Return to main program. Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Creating an Interrupt Vector When an interrupt occurs, the CPU automatically recognizes the source of the interrupt and jumps to the interrupt vector location. In this location a program is found which instructs the processor on the action(s) to be taken. Each vector location can accommodate eight instructions which correspond to a fetch packet. Such a location is known as the Interrupt Service Fetch Packet (ISFP) address. Chapter 10, Slide 19 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Interrupt Service Table The IST is a table of fetch packets that contain code for servicing the interrupts. The IST consists of 16 consecutive fetch packets. Each interrupt service fetch packet (ISFP) contains eight instructions used to service the interrupt. One of the instructions is a branch to the interrupt return pointer instruction (B IRP). The IST is located at addresses 0 h - 200 h 16 fetch packets in the table, each fetch packet is of 8 instructions of 32 bits/instruction or = 32 bytes. 16*32=512 bytes=200 h Chapter 10, Slide 20 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Creating an Interrupt Vector The following table shows the interrupt sources and associated ISFP addresses: Chapter 10, Slide 21 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Creating an Interrupt Vector Example 1: ISR fits into a single Fetch Packet (FP). Chapter 10, Slide 22 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Creating an Interrupt Vector Example 2: ISR fits into multiple successive FP’s (assuming the next interrupts are not used). Chapter 10, Slide 23 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Creating an Interrupt Vector Example 3: ISR is situated outside the interrupt vector table. 0 x 0000 RESET 0 x 0020 NMI Res 0 x 0080 INT 4 INT 5 INT 6 MVKH B ISR LDH MVC STR ZERO Branch to ISR after executing the FP ISR B IRP NOP 5 Chapter 10, Slide 24 Return from interrupt after executing the ISR Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Relocating the Vector Table In general the vector table or the section “vectors” is linked to address zero. However in many applications there is a need to change the location of the vector table. The location of the interrupt vector table is set in the. cmd file under the segment marked. vec In the C 6713 dsk. cmd file the vector table is placed at address 0 The IST, with the addresses of the ISR of the different interrupt source, can also be found in the vectors. asm file Chapter 10, Slide 25 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Relocating the Vector Table This is due to many factors such as: Moving interrupt vectors to fast memory. Having multiple vector tables for use by different tasks. Boot ROM already contained in memory starting at address 0 x 0000. Memory starting at location zero is external and hence there will be a need to move the vector table to internal memory to avoid bus conflict in shared memory system. In order to relocate the vector table, the Interrupt Service Table Pointer (ISTP) register should be set up. Chapter 10, Slide 26 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Relocating the Vector Table 31 ISTP Chapter 10, Slide 27 10 ISTB reserved Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Relocating the Vector Table Example: Relocate the ISTP to address 0 x 800. (1) The interrupt vector code located between 0 x 000 and 0 x 200 must be copied to the location 0 x 800 and 0 x 800 + 0 x 200 (0 x. A 00). (2) Initialize the ISTP. Chapter 10, Slide 28 MVKL 0 x 800, A 0 MVKH 0 x 800, A 0 MVC A 0, ISTP Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Enable Individual Interrupts (in IE Register) 31 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IE 15 IE 14 IE 13 IE 12 IE 11 IE 10 IE 9 IE 8 IE 7 IE 6 IE 5 IE 4 rsv nmie 1 R, W, +0 R, +1 To enable each int, write “ 1” to IE bit IER bits are NOT affected by the value in global interrupt enable (GIE) Example: Write some code to enable INT 7. Chapter 10, Slide 29 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Enable Individual Interrupts Method 1: Using “C” code. #include <c 6 x. h> void enable_INT 7 (void) { IER = IER | 0 x 040; } Method 2: Using assembly. _asm_set_INT 7 MVC. S 2 IER, B 0 SET. L 2 B 0, 7, 7, B 0 MVC. S 2 B 0, IER Method 3: Using the CSL. #include <csl. h> #include <csl_irq. h> IRQ_enable (IRQ_EVT_EXTINT 7) Chapter 10, Slide 30 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Enable Global Interrupt (In CS Reg. ) IER CSRGIE RESET NMI ‘C 6000 CPU INT 15 GIE IER allows the enabling or disabling of interrupts individually. GIE bit allows the enabling or disabling of interrupts globally (all at once). Note: By disabling GIE, interrupts can be prevented from occurring during initialization. Chapter 10, Slide 31 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Enable Global Interrupt Method 1: Using “C” code. #include <c 6 x. h> void enable_GIE (void) { CSR = CSRIER | 0 x 1; } Method 2: Using assembly. _asm_set_GIE MVC. S 2 CSR, B 0 SET. L 2 B 0, 0, 0, B 0 MVC. S 2 B 0, CSR Method 3: Using the CSL. #include <csl. h> #include <csl_irq. h> IRQ_global. Enable () Chapter 10, Slide 32 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Check for a Valid Signal CPU Clock (CLKOUT 1) INTx 2 cycles minimum Occurrence of Interrupt 2 cycles minimum Interrupt latched Interrupt recognized by CPU Conditions for recognition of an external interrupt: The interrupt must be held low for at least 2 cycles then high for at least two cycles. Recognition of the interrupt: The interrupts are latched on the rising edge of CLKOUT 1. The interrupt is finally recognized by the CPU one cycle after being latched. Chapter 10, Slide 33 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Interrupt Flag Register (IFR) When an interrupt is recognized, the corresponding bit in the IFR is set: e. g. if INT 7 is recognized, then IFR[7] bit is set. IFR RESET IER CSRGIE 0 INT 7 10 INT 15 0 ‘C 6000 CPU GIE Chapter 10, Slide 34 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
What Happens When an Interrupt Occurs? The corresponding bit in the IFR is set to 1 If GIE=1 (interrupts are globally enabled), and no higher priority interrupts are pending, the interrupt is serviced: Chapter 10, Slide 35 GIE is cleared to preclude other interrupts The flag bit in the IFR is cleared The return address is put in the IRP When CPU interrupt INT_n occurs, program execution jumps to byte offset 32 n in the interrupt service table (IST) (each entry in the table is eight instructions long) Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
What Happens When an Interrupt Occurs? An ISFR (Interrupt Service Fetch Packet) may contain the entire service routine, or it may branch to a larger service routine The service routine must save the CPU state on entry (save registers on stack), and restore it on exit A return from interrupt is accomplished by the assembly instruction B IRP where IRP holds the return address to the main program Chapter 10, Slide 36 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
CPU Interrupt Hardware Sequence What does the CPU do when an interrupt is recognized? CPU Action Description 0 ® IFR (bit) Clears corresponding interrupt flag bit GIE ® PGIE Save previous value of GIE 0 ® GIE Disables global interrupts Save next EP address Save return address in IRP/NRP Vector (ISTP) ® PC Loads PC with interrupt vector addr 1 ® IACK pin IACK is asserted INUM(0 -3) INUM pins display corresponding int IACK and INUM pins are only available on the C 620 x and C 670 x. Chapter 10, Slide 37 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
CPU Interrupt Hardware Sequence e. g. if INT 7 is recognized and IER[7] is set: 31 7 IFR 1 0 31 CSR 31 INT 7 -> 0 x 0800000 ADD A 0, A 1, A 2 0 x 0800004 MPY A 2, A 6, A 7 PC IRP 1 0 0 x 0800 0000 0 x 0000 2000 31 Chapter 10, Slide 38 0 0 0 x 0000 xxxx 2004 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Writing the ISR in C There are two methods of declaring an ISR: (1) Traditional method: interrupt void ISR_name (void); Notes: You need to use the interrupt keyword in order to inform the compiler that it is an ISR, and therefore to handle the necessary register preservation and use the IRP for returning from the interrupt. No arguments can be passed to the ISR. No argument can be returned. Chapter 10, Slide 39 main (void) {. . . } interrupt void ISR_name (void) {. . . } Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Writing the ISR in C (2) Using the dispatcher in DSP/BIOS: Notes: You do not need to use the interrupt keyword. Interrupt nesting of interrupt functions written in “C” is allowed. You can pass one argument. You can specify which interrupts can be nested by specifying a mask. Chapter 10, Slide 40 Insert figure Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Writing the ISR in Assembly For maskable interrupts the return from interrupt address is always stored in the Interrupt Return Pointer (IRP). For non-maskable interrupts the address is stored in the Non-maskable Return Pointer (NRP). Chapter 10, Slide 41 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Writing the ISR in Assembly _isr_function stw. . . ldh. . . (1) (2) (3) Save any registers used by the ISR on the stack Use the HWI macros, or Use the hardware interrupt dispatcher Put your ISR code here ldw. . . (1) (2) (3) b irp nop 5 Return (You can also use HWI macros) Restore Use the the HWI registers saved on the stack macros, or dispatcher It is much simpler to use the HWI dispatcher rather than doing the save and restore of registers by yourself or the HWI_enter and HWI_exit macros. Chapter 10, Slide 42 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Interrupts and the AIC 23 Codec Reading input samples from an input signal and writing output samples to generate an output signal are done by the AIC 23 codec (through the processor serial port Mc. BSP) This device includes an A/D and D/A converters. When inputting samples, the A/D converter may interrupt the processor when a valid sample is available When outputting samples, the D/A converter may interrupt the processor when it is ready to receive the next sample Chapter 10, Slide 43 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Interrupts and the AIC 23 Codec Chapter 10, Slide 44 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
The Codec Block Diagram Includes ADC DAC Anti-aliasing Filter Smoothing output filter Clock generator for the sampling rate and bit IO RLINEIN, LLINEIN – analogue line in inputs MICIN – Microphone input ROUT, LOUT – analogue output lines RHPOUT, LHPOUT – headphone output lines DOUT – the digital converted data, converted by the ADC, output serially DIN – The digital data in to be converted by the DAC, input serially
Codec Initialization
Codec Initialization
Codec Initialization
Codec Initialization
Codec Interrupt
Codec Interrupt
Interrupt Vector The following is the interrupt mapping table, specified in the vectors_intr. asm file. Only interrupt 0 and 11 are specified: . ref _c_int 00 ; entry address VEC_ENTRY. macro addr STW B 0, *--B 15 MVKL addr, B 0 MVKH addr, B 0 B B 0 LDW *B 15++, B 0 NOP 2 NOP. endm ; macro for ISR _vec_dummy: B B 3 NOP 5 . sect ". vecs". align 1024 ; aligned IST section _vectors: _vector 0: VEC_ENTRY _c_int 00 ; RESET _vector 1: VEC_ENTRY _vec_dummy ; NMI _vector 2: VEC_ENTRY _vec_dummy ; RSVD _vector 3: VEC_ENTRY _vec_dummy _vector 4: VEC_ENTRY _vec_dummy _vector 5: VEC_ENTRY _vec_dummy _vector 6: VEC_ENTRY _vec_dummy _vector 7: VEC_ENTRY _vec_dummy _vector 8: VEC_ENTRY _vec_dummy _vector 9: VEC_ENTRY _vec_dummy _vector 10: VEC_ENTRY _vec_dummy _vector 11: VEC_ENTRY _c_int 11 ; ISR address _vector 12: VEC_ENTRY _vec_dummy _vector 13: VEC_ENTRY _vec_dummy _vector 14: VEC_ENTRY _vec_dummy _vector 15: VEC_ENTRY _vec_dummy The mapping of the codec (MCBSP) interrupt to interrupt 11 is done separately in function comm_intr(), called within the main program
Codec Data Obtained
Interfacing the Codec and the Processor The serial port Mc. BSP 0 is configured to act as a control channel. Through this channel the processor sets the codec to function in the desired mode, e. g. To operate in stereo mode receiving 2 x 16 bits samples Setting the desired sampling rate The serial port Mc. BSP 1 is configured to function as the data channel, sending data to the codec, and receiving data from it Chapter 10, Slide 54 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Interrupts and the AIC 23 Codec The first word transmitted by AIC 23 is the left channel sample, followed by the right channel sample The 32 -bit word received by Mc. BSP 1 from the codec contains the left sample in the upper 16 bits and the right sample in the lower 16 bits. The 16 -bit samples are integers in 2’s complement format Words sent from the Mc. BSP 1 to the codec, must have the same format It is the codec which generates a sync pulse at the beginning of a sample pair, and the shift clock to send/receive the samples serially Chapter 10, Slide 55 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Codec Data Obtained
Multi-channel Buffered Serial Port (Mc. BSP) The Mc. BSP serves as a serial data channel to the DSP Through it, data can be written out or read in by the DSP The Mc. BSP can generate receive and transmit interrupt to the CPU: A receive interrupt when it has data for the CPU A transmit interrupt when it is ready for the next data item to be sent On the DSK, the serial port uses an external clock from the codec to shift data in and out serially Chapter 10, Slide 57 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Mc. BSP Block Diagram Chapter 10, Slide 58 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Mc. BSP Transmit Block Diagram The CPU writes a word into the Data Transmit Register (DXR) The word is loaded into the Transmit Shift Register (XSR), from where it is being shifted out (by the transmit clock) The Mc. BSP sends an interrupt request to the CPU, after the data has been loaded into the XSR, signaling that it is ready to transmit another word Chapter 10, Slide 59 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Mc. BSP Receive Block Diagram Data bits are shifted into the Receive Shift Register (RSR) using the receive clock. When all word bits are in, the RSR register is loaded into the Receive Buffer Register (RBR), and then to the Data Receive Register (DRR) Then, the Mc. BSP sends an interrupt request to the CPU, indicating that a data word is available for reading Chapter 10, Slide 60 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Codec Interface AIC 23 Mc. BSP 0 Voice Channel DRR DXR ADC gain CLKR CLKX DAC gain Fs = 8 k. Hz Data Channel clock AIC 23: Has two channels (voice & data), only the voice was used on DSK Receives all commands and exchanges data serially via Mc. BSP 0 Driven by ext. 8 k. Hz clock on DSK board. It drives ‘C 6713 serial port 0 (Mc. BSP 0) shift clocks. 4 k. Hz? 8 k. Hz sample rate allows maximum sine wave of ______ Chapter 10, Slide 61 Looking closer at the. Dr. Mc. BSP. . . Bristol University, Naim Dahnoun, (c) Texas Instruments 2002
BSL Codec Functions AIC 23 Mc. BSP 0 Voice Channel DRR DXR ADC gain CLKR CLKX DAC gain Fs = 8 k. Hz Data Channel clock AIC 23 BSL (DSK Board Support Library) AIC 23_open() reserves resource and returns handle AIC 23_config() configures Mc. BSP 0 and AIC 23_read() reads from AIC 23 ADC thru Mc. BSP 0 receive AIC 23_write() writes to AIC 23 DAC thru Mc. BSP 0 transmit Chapter 10, Slide 62 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Sending Data from the CPU to AIC 23 DAC Codec Interface CPU Mc. BSP 0 AIC 23 sine xmit D/A speaker 150 MHz 8 k. Hz sample clock Codec accepts samples at the sampling rate (8 k. Hz) It signals the Mc. BSP when it is ready to receive another sample
XINT 0 Interrupt Codec Interface CPU Mc. BSP 0 AIC 23 speaker sine xmit D/A XINT 0 8 k. Hz sample clock When Mc. BSP needs another sample, it issues XINT 0 HWI XINT 0 should occur at 8 k. Hz (codec sample rate) How do we make CPU wait? How do you make an HWI function? Use loop: while(1); Use config tool
Writing samples to the AIC 23 Codec The 32 -bit words are sent to the codec by the BSL function DSK 6713_AIC 23_write() This function Polls the Mc. BSP 1 XRDY bit, and does not sent the data if the bit is not set. It sends the sample word by writing it to the Data Transmit Register (DXR) of Mc. BSP 1 if XRDY bit is set The corresponding code is (all functions in CSL Library) Chapter 10, Slide 65 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Reading samples from the AIC 23 Codec 32 -bit words are read from the codec by the BSL function DSK 6713_AIC 23_read() This function Polls the Mc. BSP 1 RRDY bit, and does not read the data if the bit is not set. It reads the sample word from the Data Receive Register (DRR) of Mc. BSP 1 if RRDY bit is set The corresponding code is (all functions are in CSL Library) : Chapter 10, Slide 66 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Interrupts and the AIC 23 Codec Files for use with the codec: Chapter 10, Slide 67 C 6713 dsk. cmd – sets up the memory map C 6 x. h – defines some of the registers like IER, CSR in C: tic 6000cgtoolsinclude C 6713 dsk. h in C: tic 6000dsk 6713include – header file that defines addresses of external memory interface, the serial ports, etc IML, IMH defined here C 6713 interrupts. h – contains init functions for interrupt C 6713 dskinit. h – header file with the function prototypes C 6713 dskinit. c – functions to initialize the DSK, the codec, serial ports, and for input/output. Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Setting ISR for XINT 0 (Mc. BSP 0 Transmit) In vectors. asm Interrupt 0 is set for reset – ISR c_int 00 Interrupt 11 is set for ISR c_int 11 In c 6 xdskinit. c interrupt 11 is attached to transmit signal XINT 0 of the serial port of ‘c 6713 (done in comm_intr() using IRQ_map() function) Each time an interrupt occurs at XINT 0 (connected to the codec sampling clock), the ISR c_int 11 is executed This function is defined in the main C program interrupt void c_int 11() //interrupt service routine { }
Setting ISR for XINT 0 (Mc. BSP 0 Transmit) For example, the ISR for reading an input sample from the ADC and outputting it to the DAC is interrupt void c_int 11() //interrupt service routine { int sample_data; sample_data = input_sample(); //input data output_sample(sample_data); //output data return; }
Sending Input Samples Out using Interrupt #include "dsk 6713_aic 23. h" //codec-DSK support file Uint 32 fs=DSK 6713_AIC 23_FREQ_8 KHZ; //set sampling rate void main() { comm_intr(); //init DSK, codec, Mc. BSP while(1); //infinite loop } interrupt void c_int 11() //interrupt service routine { short sample_data; sample_data = input_sample(); //input data output_sample(sample_data); //output data }
Sending Input Samples Out using Interrupt The main program initializes the DSK, the Codec and the Mc. BSP, and then goes into an infinite waiting loop Each time a sample is available, the c_int 11 function is executed, reading an input sample and sending it out Rather than being engaged in an infinite waiting loop, the main program can perform other tasks. It will be interrupted each time an input sample is available
Polling with the AIC 23 Codec Reading input samples from an input signal and writing output samples to generate an output signal may also be accomplished by polling and the processor serial port The register used for polling is the Serial Port Control Register (SPCR) For reading, test bit 1 (second LSB) of the register to see if the port is ready to be read. This is done by doing an AND of the SPCR with 0 x 2. For writing, AND SPCR with 0 x 20000 to test bit 17, the transmit ready bit. Chapter 10, Slide 72 Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002
Sending Input Samples Out using Polling #include "DSK 6713_AIC 23. h" //codec-DSK file support Uint 32 fs=DSK 6713_AIC 23_FREQ_8 KHZ; //sampling rate void main() { short sample_data; comm_poll(); //init DSK, codec, Mc. BSP while(1) //infinite loop { sample_data = input_sample(); //input sample output_sample(sample_data); //output sample } }
Sending Input Samples Out using Polling The polling flag is set by comm_poll(), and then within input sample RRDY bit is polled, and within output sample XRDY bit is polled (see these functions in c 6713 dskinit. c) Uint 32 input_sample() //for 32 -bit input { short CHANNEL_data; if (poll) while(!MCBSP_rrdy(DSK 6713_AIC 23_DATAHANDLE)); //if ready to receive AIC_data. uint=MCBSP_read(DSK 6713_AIC 23_DATAHANDLE); //read data return(AIC_data. uint); } void output_sample(int out_data) //for out to Left and Right channels { short CHANNEL_data; AIC_data. uint=out_data; //32 -bit data -->data structure if (poll) while(!MCBSP_xrdy(DSK 6713_AIC 23_DATAHANDLE)); //if ready to transmit MCBSP_write(DSK 6713_AIC 23_DATAHANDLE, AIC_data. uint); } //write/output data
Sending Input Samples Out using Polling Unlike the implementation with interrupt, when using polling, the main program is always busy waiting for input samples. The main program cannot be engaged in other tasks Polling is done in input_sample and output_sample functions The polling flag is set by comm_poll(), and then within input sample RRDY bit is polled, and within output sample XRDY bit is polled (see these functions in c 6713 dskinit. c)
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