History of Embedded Systems Discussion 0 1 Bell
![History of Embedded Systems Discussion 0. 1 History of Embedded Systems Discussion 0. 1](https://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-1.jpg)
History of Embedded Systems Discussion 0. 1
![Bell Labs Museum The First Point-Contact Transistor 1947 Bell Labs Museum The First Point-Contact Transistor 1947](http://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-2.jpg)
Bell Labs Museum The First Point-Contact Transistor 1947
![Bell Labs The First Junction Transistor 1951 M 1752 Outside the Lab model Bell Labs The First Junction Transistor 1951 M 1752 Outside the Lab model](http://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-3.jpg)
Bell Labs The First Junction Transistor 1951 M 1752 Outside the Lab model
![Texas Instrument’s First IC -- 1958 Jack Kilby Robert Noyce Fairchild Intel Texas Instrument’s First IC -- 1958 Jack Kilby Robert Noyce Fairchild Intel](http://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-4.jpg)
Texas Instrument’s First IC -- 1958 Jack Kilby Robert Noyce Fairchild Intel
![Embedded System A single-purpose, programmable, digital system Embedded System A single-purpose, programmable, digital system](http://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-5.jpg)
Embedded System A single-purpose, programmable, digital system
![1961 – Unimate Robot at GM 1961 – Unimate Robot at GM](http://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-6.jpg)
1961 – Unimate Robot at GM
![1965: PDP-8 first mass-produced Mini 1965: PDP-8 first mass-produced Mini](http://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-7.jpg)
1965: PDP-8 first mass-produced Mini
![Electronics, Volume 38, Number 8, April 19, 1965 Electronics, Volume 38, Number 8, April 19, 1965](http://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-8.jpg)
Electronics, Volume 38, Number 8, April 19, 1965
![](http://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-9.jpg)
![](http://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-10.jpg)
![Moore’s law • Wow – This growth rate is hard to imagine, most people Moore’s law • Wow – This growth rate is hard to imagine, most people](http://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-11.jpg)
Moore’s law • Wow – This growth rate is hard to imagine, most people underestimate – How many ancestors do you have from 20 generations ago • i. e. , roughly how many people alive in the 1500’s did it take to make you? • 220 = more than 1 million people
![Graphical illustration of Moore’s law 1981 1984 1987 1990 1993 1996 1999 2002 10, Graphical illustration of Moore’s law 1981 1984 1987 1990 1993 1996 1999 2002 10,](http://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-12.jpg)
Graphical illustration of Moore’s law 1981 1984 1987 1990 1993 1996 1999 2002 10, 000 transistors 150, 000 transistors Leading edge chip in 1981 Leading edge chip in 2002 • Something that doubles frequently grows more quickly than most people realize! – A 2002 chip can hold about 15, 000 1981 chips inside itself
![1968 – Apollo Guidance Computer 1968 – Apollo Guidance Computer](http://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-13.jpg)
1968 – Apollo Guidance Computer
![Intel 4004 source: Computer Museum Intel 4004 source: Computer Museum](http://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-14.jpg)
Intel 4004 source: Computer Museum
![January 1975 cover of Popular Electronics http: //www. blinkenlights. com/pc. shtml January 1975 cover of Popular Electronics http: //www. blinkenlights. com/pc. shtml](http://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-15.jpg)
January 1975 cover of Popular Electronics http: //www. blinkenlights. com/pc. shtml
![1978 – Industrial Holographics 1978 – Industrial Holographics](http://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-16.jpg)
1978 – Industrial Holographics
![Time's Man of the Year (1982) Time's Man of the Year (1982)](http://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-17.jpg)
Time's Man of the Year (1982)
![1985 – Motorola introduces the 68 HC 11 microcontroller 1985 – Motorola introduces the 68 HC 11 microcontroller](http://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-18.jpg)
1985 – Motorola introduces the 68 HC 11 microcontroller
![1997 – Motorola introduces the 68 HC 12/HCS 12 microcontroller Additional PWM and CAN 1997 – Motorola introduces the 68 HC 12/HCS 12 microcontroller Additional PWM and CAN](http://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-19.jpg)
1997 – Motorola introduces the 68 HC 12/HCS 12 microcontroller Additional PWM and CAN interfaces
![Develops WHYP – a subroutine-threaded Forth for the 68 HC 12 Develops WHYP – a subroutine-threaded Forth for the 68 HC 12](http://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-20.jpg)
Develops WHYP – a subroutine-threaded Forth for the 68 HC 12
![Chuck Moore, the inventor of Forth, reading Haskell’s WHYP book Chuck Moore, the inventor of Forth, reading Haskell’s WHYP book](http://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-21.jpg)
Chuck Moore, the inventor of Forth, reading Haskell’s WHYP book
![1975 – Signetics invents the FPLA 1975 – Signetics invents the FPLA](http://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-22.jpg)
1975 – Signetics invents the FPLA
![1978 – MMI introduces the PAL 1978 – MMI introduces the PAL](http://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-23.jpg)
1978 – MMI introduces the PAL
![1983 – AMD introduces the 22 V 10 1984 – Lattice introduces the GAL 1983 – AMD introduces the 22 V 10 1984 – Lattice introduces the GAL](http://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-24.jpg)
1983 – AMD introduces the 22 V 10 1984 – Lattice introduces the GAL – an electrically erasable PAL
![1985 – Xilinx introduces the LCA (Logic Cell Array) The Xilinx XC 3000 CLB 1985 – Xilinx introduces the LCA (Logic Cell Array) The Xilinx XC 3000 CLB](http://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-25.jpg)
1985 – Xilinx introduces the LCA (Logic Cell Array) The Xilinx XC 3000 CLB (configurable logic block).
![1991 – Xilinx introduces the XC 4000 Architecture Programmable Interconnect Configurable Logic Blocks (CLBs) 1991 – Xilinx introduces the XC 4000 Architecture Programmable Interconnect Configurable Logic Blocks (CLBs)](http://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-26.jpg)
1991 – Xilinx introduces the XC 4000 Architecture Programmable Interconnect Configurable Logic Blocks (CLBs) I/O Blocks (IOBs) XC 4003 contained 440, 000 transistors 0. 7 -micron process
![XC 4000 E/X Configurable Logic Blocks • 2 Four-input function generators (Look Up Tables) XC 4000 E/X Configurable Logic Blocks • 2 Four-input function generators (Look Up Tables)](http://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-27.jpg)
XC 4000 E/X Configurable Logic Blocks • 2 Four-input function generators (Look Up Tables) G 4 - 16 x 1 RAM or G 3 Logic function G 2 G 1 • 2 Registers - Each can be configured as Flip F 4 Flop or Latch F 3 - Independent F 2 F 1 clock polarity - Synchronous and asynchronous Set/Reset C 1 C 2 C 3 C 4 H 1 DIN S/R EC S/R Control DIN G Func. Gen. YQ 1 EC RD G' H' Y S/R Control DIN SD F' G' D Q XQ H' H' K Q D H' H Func. Gen. F Func. Gen. SD F' G' F' 1 EC RD X
![Look Up Tables • Combinatorial Logic is stored in 16 x 1 SRAM Look Look Up Tables • Combinatorial Logic is stored in 16 x 1 SRAM Look](http://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-28.jpg)
Look Up Tables • Combinatorial Logic is stored in 16 x 1 SRAM Look Up Tables (LUTs) in a CLB Look Up Table 4 -bit address • Example: Combinatorial Logic A B C D A B Z C D w Capacity is limited by number of inputs, not complexity w Choose to use each function generator as 4 input logic (LUT) or as high speed sync. dual port RAM WE G 4 G 3 G 2 G 1 G Func. Gen. 0 0 0 0 0 1 1 0 0 0 1 0 1 Z 0 0 0 1 1 1 . . . 1 1 1 1 0 0 1 1 0 1 0 0 0 1 4 2(2 ) = 64 K !
![1998 – Xilinx introduces the Virtex®™ FPGA family 0. 25 -micron process 1998 – Xilinx introduces the Virtex®™ FPGA family 0. 25 -micron process](http://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-29.jpg)
1998 – Xilinx introduces the Virtex®™ FPGA family 0. 25 -micron process
![2003 – Xilinx introduces the Spartan®™-3 family of products Very low cost World’s first 2003 – Xilinx introduces the Spartan®™-3 family of products Very low cost World’s first](http://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-30.jpg)
2003 – Xilinx introduces the Spartan®™-3 family of products Very low cost World’s first 90 nm FPGA
![](http://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-31.jpg)
![Xilinx will release the world’s first one-billion transistor device this year x Xilinx will release the world’s first one-billion transistor device this year x](http://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-32.jpg)
Xilinx will release the world’s first one-billion transistor device this year x
![Logic Implementations • Fixed (ASICs) -- $12 billion market • Programmable (PLDs) -- $3. Logic Implementations • Fixed (ASICs) -- $12 billion market • Programmable (PLDs) -- $3.](http://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-33.jpg)
Logic Implementations • Fixed (ASICs) -- $12 billion market • Programmable (PLDs) -- $3. 5 billion market – CPLDs – FPGAs
![Advantages of ASICs • Lower costs for very large volumes • Highest performance capabilities Advantages of ASICs • Lower costs for very large volumes • Highest performance capabilities](http://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-34.jpg)
Advantages of ASICs • Lower costs for very large volumes • Highest performance capabilities
![Advantages of PLDs • • • Flexibility during design cycle Available – no long Advantages of PLDs • • • Flexibility during design cycle Available – no long](http://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-35.jpg)
Advantages of PLDs • • • Flexibility during design cycle Available – no long lead times No NRE costs Low inventory Can be modified after delivery
![PLD and ASIC cost cross-over point Nick Tredennick Gilder Technology Report PLD and ASIC cost cross-over point Nick Tredennick Gilder Technology Report](http://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-36.jpg)
PLD and ASIC cost cross-over point Nick Tredennick Gilder Technology Report
![PLD and ASIC cost cross-over points (dots) with time Nick Tredennick Gilder Technology Report PLD and ASIC cost cross-over points (dots) with time Nick Tredennick Gilder Technology Report](http://slidetodoc.com/presentation_image/ccd5ae9ef014eafe5068fda4d7305fe2/image-37.jpg)
PLD and ASIC cost cross-over points (dots) with time Nick Tredennick Gilder Technology Report
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