Embedded Systems Design Optimization Challenges Paul Pop Embedded

Embedded Systems Design: Optimization Challenges Paul Pop Embedded Systems Lab (ESLAB) Linköping University, Sweden 1 of 1/34 14

Outline à Embedded systems § Example area: automotive electronics § Embedded systems design § Optimization problems § Fault-tolerant mapping and scheduling § Voltage scaling § Communication delay analysis § Assessment and message 2 of 2/34 14

Embedded Systems General purpose systems Embedded systems Microprocessor market shares 3 of 3/34 14

Example Area: Automotive Electronics § What is “automotive electronics”? § Vehicle functions implemented with electronics § Body electronics § System electronics: chassis, engine § Information/entertainment 4 of 4/34 14

Automotive Electronics Market Size 1400 Cost of Electronics / Car ($) 1200 1000 800 2006: 25% of the total cost of a car will be electronics 600 400 200 0 1998 Market 8. 9 ($billions) 1999 10. 5 2000 2001 2002 2003 2004 2005 13. 1 14. 1 15. 8 17. 4 19. 3 21. 0 90% of future innovations in vehicles: based on electronic embedded systems 5 of 5/34 14

Automotive Electronics Platform Example Source: Expanding automotive electronic systems, IEEE Computer, Jan. 2002 6 of 6/34 14

Outline § Embedded systems § Example area: automotive electronics à Embedded systems design § Optimization problems § Fault-tolerant mapping and scheduling § Voltage scaling § Communication delay analysis § Assessment and message 7 of 7/34 14

Embedded Systems Design §Growing complexity §Constraints §Time, energy, size §Cost, time-to-market §Safety, reliability System platform Estimation: exec. time System model System-level design tasks § Mapping and scheduling § Voltage scaling §Heterogeneous §Hardware components §Comm. protocols Model of system implementation Software Hardware synthesis Analysis § Communication delay analysis 8 of 8/34 14

Embedded System Design, Cont. § Goal: automated design optimization techniques § § Successfully manage the complexity of embedded systems Meet the constraints imposed by the application domain Shorten the time-to-market Reduce development and manufacturing costs Optimization: the key to successful design 9 of 9/34 14

Outline § Embedded systems § Example area: automotive electronics § Embedded systems design à Optimization problems § Fault-tolerant mapping and scheduling § Voltage scaling § Communication delay analysis § Assessment and message 10 of 10/34 14

Optimization Problems 1. Mapping and scheduling 1. 1 Mapping to minimize communication 1. 2 Mapping and scheduling 1. 3 Fault-tolerant mapping and scheduling 2. Voltage scaling 2. 1 Continuous voltage scaling 2. 2 Discrete voltage scaling 3. Communication delay analysis 11 of 11/34 14

Problem #1. 1: Mapping è Given § Application: set of interacting processes § Platform: set of nodes m 1 P 22 m 3 ç Determine § Mapping of processes to nodes § Such that the communication is minimized P 11 N 1 m 2 P 33 P 44 m 4 N 2 Þ Assessment § Optimal solutions even for large problem sizes 12 of 12/34 14

Problem #1. 2: Mapping and Scheduling è Given m 1 § Application: set of interacting processes § Platform: set of nodes § Timing constraints: deadlines P 1 P 2 m 3 ç Determine § Mapping of processes and messages § Schedule tables for processes and messages N 1 m 2 P 3 P 4 m 4 N 2 § Such that the timing constraints are satisfied P 1 N 1 Schedule table P 4 P 2 N 2 Bus S 2 S 1 m 1 Deadline P 3 m 2 m 3 m 4 13 of 13/34 14

Problem #1. 2: Assessment § Scheduling is NP-complete even in simpler context § D. Ullman, “NP-Complete Scheduling Problems”, Journal of Computer Systems Science, volume 10, pages 384– 393, 1975. § ILP formulation § Can’t obtain optimal solutions for large problem sizes § Alternative: divide the problem § Scheduling § Heuristic: List scheduling § Mapping § Simulated annealing § Tabu-search § Problem-specific greedy algorithms 14 of 14/34 14

Fault-Tolerant Mapping and Scheduling Transient faults . . . TDMA bus: TTP Processes: Re-execution and replication Schedule tables Messages: Fault-tolerant Schedule tables protocol 15 of 15/34 14

Fault-Tolerance Techniques 2 N 1 P 1 P 1 N 2 N 3 Re-execution P 1 N 1 P 1 N 2 P 1 P 1 Replication Re-executed replicas 16 of 16/34 14

Problem #1. 3: Formulation è Given § § Application: set of interacting processes Platform: set of nodes Timing constraints: deadlines Fault model: number of transient faults in the system period ç Determine Fault-model: transient faults § Mapping of processes and messages § Schedule tables for processes and messages § Fault-tolerance policy assignment § Such that the timing constraints are satisfied Application: set of process graphs Architecture: time-triggered system 17 of 17/34 14

Fault-Tolerance Policy Assignment Deadline P 1 P 2 P 4 P 4 P 11 P 2 TTP S 11 S 22 P 4 P 3 P 32 m 2 P 3 P 1 m 1 P 3 P 2 m 3 P 4 P 3 Met. Missed P 4 Missed Optimization of fault-tolerance policy assignment m 3 P 1 m 12 m 1 m 2 N 22 m 2 TTP S 1 S 2 N 11 No fault-tolerance: application crashes P 3 N 2 m 2 N 1 P 4 P 1 P 2 P 3 P 4 N 1 N 2 40 50 60 80 40 50 1 N 2 18 of 18/34 14

Tabu-Search: Policy Assignment & Mapping Design transformations m 2 P 3 P 1 m 1 P 2 m 3 P 4 P 1 P 2 P 3 P 4 N 1 N 2 40 50 60 75 40 50 1 N 2 19 of 19/34 14

Problem #2: Voltage Scaling §GSM Phone: §Search §Radio link control §Talking §MP 3 Player Power constraints 70 60 50 Battery power Chip power 40 §Digital Camera: §Take photo §Restore photo 30 20 10 0 1997 1999 2002 2005 2008 2011 Timing constraints 20 of 20/34 14

Problem #2: Voltage Scaling Different voltages: different frequencies CPU Vdd Energy/speed trade-offs: varying the voltages f 1 f 2 f 3 Vbs Power P Slack t 1 t 2 t 3 t deadline t 1 t 2 t t 3 deadline Mapping and scheduling: given (fastest freq. ) 21 of 21/34 14

Problem #2. 1: Continuous Voltage Scaling è Given § Application: set of interacting processes § Platform: set of nodes, each having supply voltage (Vdd) and body bias voltage (Vbs) inputs § Mapping and schedule table (including timing constraints) Vdd Vbs CPU 1 t 0 t 5 Bus Architecture and mapping t 2 CPU 2 t 1 t 3 Vdd Vbs CPU 3 Vdd Vbs t 4 Schedule table / processor P Slack t 1 t 2 t 3 t deadline 22 of 22/34 14

Problem #2. 1: Continuous Voltage Scaling ç Determine § Voltage levels Vdd and Vbs for each process § Such that system energy is minimized and § Deadlines are satisfied Þ Assessment P § Convex nonlinear problem Height: Slackgood precision § Polynomial time solvable with an arbitrary Input voltage level § A. Andrei, “Overhead-Conscious Voltage Selection for Dynamic and t t 2 of 3 1 Leakage Energy Reduction Time-Constrained Systems”, technical deadline report, Linköping University, 2004 Area: energy P t 1 t 2 t t 3 deadline Output 23 of 23/34 14

Problem #2. 1: Formulation § Minimize energy § E[t 0] + E[t 1] + E[t 2] + E_OH[t 1 -t 2] Energy due to processes Overhead due to voltage changes § Such that § Tstart[t 0] + Texe[t 0] Tstart[t 1] § Tstart[t 1] + Texe[t 1] + Toh[t 1 -t 2] Tstart[t 2] Precedence relationships § Tstart[t 2] + Texe[t 2] DL[t 2] Deadlines 24 of 24/34 14

Problem #2. 2: Discrete Voltage Scaling § Problem formulation è Given discrete execution frequencies Processors can operate using a frequency from a fixed discrete set Changing the frequency incurs a delay and an energy penalty ç Determine the set of frequencies for each task § Such that system energy is minimized and § Deadlines are satisfied Discrete P deadline f 2 f 3 t 1 f 3 t 2 f 2 t 3 f 1 t 25 of 25/34 14

Problem #2. 2: Example è Given § 1 processor: f {50, 100, 150} MHz § 3 processes § t 1: P={10, 20, 30} m. W, dl=1 ms, NC=100 cycles § t 2: P={12, 22, 32} m. W, dl=1. 5 ms , NC=100 cycles § t 3: P={15, 25, 35} m. W, dl=2 ms , NC=100 cycles § Schedule: execution order is t 1, t 2, t 3 ç Determine § For each process, number of clock cycles to be executed at each frequency § such that the energy is minimized 26 of 26/34 14

Problem #2. 2: Example, Cont. Þ Assessment: § Strongly NP-hard problem § The frequencies are now a set of integers; identical to: § P. De, “Complexity of the Discrete Time-Cost Tradeoff Problem for Project Networks”, Operations Research, 45(2): 302– 306, March 1997. § MILP formulation for the optimal solution Each task has to execute the given number of cycles Task execution time Precedence constraints Deadline constraints Minimize energy 27 of 27/34 14

Embedded Systems Design System model System platform Estimation: exec. time §Communication protocols System-level design tasks Mapped and scheduled model Software Hardware synthesis Analysis § Communication delay analysis 28 of 28/34 14

Problem #3: Flex. Ray Analysis § Flex. Ray communication protocol § Becoming de-facto standard in automotive electronics § BMW, Daimler. Chrysler, General Motors, Volkswagen, Bosch, Motorola, Philips § Deterministic data transmission, fault-tolerant, high data-rate § Problem è Given Worst-case communication delay § Application: set of interacting processes § Platform: set of nodes connected by Flex. Ray S Mapping and. . . § Implementation: scheduling. R ç Determine Communication protocol: Flex. Ray § Worst-case communication delays for messages 29 of 29/34 14

Problem #3: Flex. Ray Analysis, Cont. Bus cycle Static Dynamic Generalized Time-division multiple access Statically assigned m 1 m 2 m 3 Off-line: Schedule table Static Dynamic Flexible Time-division multiple access Arrive dynamically m 7 m 4 m 5 m 6 Off-line: Worstcase analysis 30 of 30/34 14

Problem #3: Formulation and Example è Given Priority m 4 § Flex. Ray bus § Length of the static phase § Length of the dynamic phase m 7 m 6 § Dynamically arriving messages § Priorities m 5 ç Determine for each message Analyze this! § Worst-case communication delay Static Dynamic m 4 m 7 Fixed size bin Static Dynamic m 6 Static Dynamic m 5 Bin covering: two bins 31 of 31/34 14

Problem #3: Assessment § ”Classic” bin covering problem è Given § Set of bins of fixed integer size § Set of items of integer size ç Determine § Maximum number of bins that can be filled with the items Þ Assessment § Asymptotic fully polynomial time approximation § Flex. Ray dynamic phase analysis ≠ ”classic” bin covering § Bins have an upper limit: size of the dynamic phase § Assessment § Approximation algorithm does not exist § MILP formulation feasible up to 60 messages Wanted: better solution 32 of 32/34 14

Outline § Embedded systems § Example area: automotive electronics § Embedded systems design § Optimization problems § Fault-tolerant mapping and scheduling § Voltage scaling § Communication delay analysis à Assessment and message 33 of 33/34 14

Message § Optimization § Key to successful embedded systems design § Challenges § Classify the problems § Divide the problem into sub-problems § Formulate the problems § Solve the problems optimally § Fast and accurate heuristics for specific problems 34 of 34/34 14