CP416 VLSI System Design Lecture 3 DC Transient

CP-416 VLSI System Design Lecture 3: DC & Transient Response Engr. Waqar Ahmad 4: DC and Transient Response UET, Taxila 1

Outline q q DC Response Logic Levels and Noise Margins Transient Response Delay Estimation 4: DC and Transient Response CMOS VLSI Design 2

Activity 1) 2) 3) 4) 5) 6) If the width of a transistor increases, the current will increase decrease not change If the length of a transistor increases, the current will increase decrease not change If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change If the width of a transistor increases, its gate capacitance will increase decrease not change If the length of a transistor increases, its gate capacitance will increase decrease not change If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change 4: DC and Transient Response CMOS VLSI Design 3

Activity 1) 2) 3) 4) 5) 6) If the width of a transistor increases, the current will increase decrease not change If the length of a transistor increases, the current will increase decrease not change If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change If the width of a transistor increases, its gate capacitance will increase decrease not change If the length of a transistor increases, its gate capacitance will increase decrease not change If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change 4: DC and Transient Response CMOS VLSI Design 4

DC Response q DC Response: Vout vs. Vin for a gate q Ex: Inverter – When Vin = 0 -> Vout = VDD – When Vin = VDD -> Vout = 0 – In between, Vout depends on transistor size and current – By KCL, must settle such that Idsn = |Idsp| – We could solve equations – But graphical solution gives more insight 4: DC and Transient Response CMOS VLSI Design 5

Transistor Operation q Current depends on region of transistor behavior q For what Vin and Vout are n. MOS and p. MOS in – Cutoff? – Linear? – Saturation? 4: DC and Transient Response CMOS VLSI Design 6

n. MOS Operation Cutoff Vgsn < 4: DC and Transient Response Linear Vgsn > Saturated Vgsn > Vdsn < Vdsn > CMOS VLSI Design 7

n. MOS Operation Cutoff Vgsn < Vtn 4: DC and Transient Response Linear Vgsn > Vtn Saturated Vgsn > Vtn Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn CMOS VLSI Design 8

n. MOS Operation Cutoff Vgsn < Vtn Linear Vgsn > Vtn Saturated Vgsn > Vtn Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn Vgsn = Vin Vdsn = Vout 4: DC and Transient Response CMOS VLSI Design 9

n. MOS Operation Cutoff Vgsn < Vtn Vin < Vtn Linear Vgsn > Vtn Vin > Vtn Vdsn < Vgsn – Vtn Vout < Vin - Vtn Saturated Vgsn > Vtn Vin > Vtn Vdsn > Vgsn – Vtn Vout > Vin - Vtn Vgsn = Vin Vdsn = Vout 4: DC and Transient Response CMOS VLSI Design 10

p. MOS Operation Cutoff Vgsp > 4: DC and Transient Response Linear Vgsp < Saturated Vgsp < Vdsp > Vdsp < CMOS VLSI Design 11

p. MOS Operation Cutoff Vgsp > Vtp 4: DC and Transient Response Linear Vgsp < Vtp Saturated Vgsp < Vtp Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp CMOS VLSI Design 12

p. MOS Operation Cutoff Vgsp > Vtp Vgsp = Vin - VDD Linear Vgsp < Vtp Saturated Vgsp < Vtp Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp < 0 Vdsp = Vout - VDD 4: DC and Transient Response CMOS VLSI Design 13

p. MOS Operation Cutoff Vgsp > Vtp Vin > VDD + Vtp Linear Vgsp < Vtp Vin < VDD + Vtp Vdsp > Vgsp – Vtp Vout > Vin - Vtp Vgsp = Vin - VDD Vtp < 0 Saturated Vgsp < Vtp Vin < VDD + Vtp Vdsp < Vgsp – Vtp Vout < Vin - Vtp Vdsp = Vout - VDD 4: DC and Transient Response CMOS VLSI Design 14

I-V Characteristics q Make p. MOS is wider than n. MOS such that bn = bp 4: DC and Transient Response CMOS VLSI Design 15

Current vs. Vout, Vin 4: DC and Transient Response CMOS VLSI Design 16

Load Line Analysis q For a given Vin: – Plot Idsn, Idsp vs. Vout – Vout must be where |currents| are equal in 4: DC and Transient Response CMOS VLSI Design 17

Load Line Analysis q Vin = 0 4: DC and Transient Response CMOS VLSI Design 18

Load Line Analysis q Vin = 0. 2 VDD 4: DC and Transient Response CMOS VLSI Design 19

Load Line Analysis q Vin = 0. 4 VDD 4: DC and Transient Response CMOS VLSI Design 20

Load Line Analysis q Vin = 0. 6 VDD 4: DC and Transient Response CMOS VLSI Design 21

Load Line Analysis q Vin = 0. 8 VDD 4: DC and Transient Response CMOS VLSI Design 22

Load Line Analysis q Vin = VDD 4: DC and Transient Response CMOS VLSI Design 23

Load Line Summary 4: DC and Transient Response CMOS VLSI Design 24

DC Transfer Curve q Transcribe points onto Vin vs. Vout plot 4: DC and Transient Response CMOS VLSI Design 25

Operating Regions q Revisit transistor operating regions Region n. MOS p. MOS A B C D E 4: DC and Transient Response CMOS VLSI Design 26

Operating Regions q Revisit transistor operating regions Region n. MOS p. MOS A Cutoff Linear B Saturation Linear C Saturation D Linear Saturation E Linear Cutoff 4: DC and Transient Response CMOS VLSI Design 27

Beta Ratio q If bp / bn 1, switching point will move from VDD/2 q Called skewed gate q Other gates: collapse into equivalent inverter 4: DC and Transient Response CMOS VLSI Design 28

Noise Margins q How much noise can a gate input see before it does not recognize the input? 4: DC and Transient Response CMOS VLSI Design 29

Logic Levels q To maximize noise margins, select logic levels at 4: DC and Transient Response CMOS VLSI Design 30

Logic Levels q To maximize noise margins, select logic levels at – unity gain point of DC transfer characteristic 4: DC and Transient Response CMOS VLSI Design 31

Transient Response q DC analysis tells us Vout if Vin is constant q Transient analysis tells us Vout(t) if Vin(t) changes – Requires solving differential equations q Input is usually considered to be a step or ramp – From 0 to VDD or vice versa 4: DC and Transient Response CMOS VLSI Design 32

Inverter Step Response q Ex: find step response of inverter driving load cap 4: DC and Transient Response CMOS VLSI Design 33

Inverter Step Response q Ex: find step response of inverter driving load cap 4: DC and Transient Response CMOS VLSI Design 34

Inverter Step Response q Ex: find step response of inverter driving load cap 4: DC and Transient Response CMOS VLSI Design 35

Inverter Step Response q Ex: find step response of inverter driving load cap 4: DC and Transient Response CMOS VLSI Design 36

Inverter Step Response q Ex: find step response of inverter driving load cap 4: DC and Transient Response CMOS VLSI Design 37

Inverter Step Response q Ex: find step response of inverter driving load cap 4: DC and Transient Response CMOS VLSI Design 38

Delay Definitions q tpdr: q tpdf: q tpd: q tr : q tf: fall time 4: DC and Transient Response CMOS VLSI Design 39

Delay Definitions q tpdr: rising propagation delay – From input to rising output crossing VDD/2 q tpdf: falling propagation delay – From input to falling output crossing VDD/2 q tpd: average propagation delay – tpd = (tpdr + tpdf)/2 q tr: rise time – From output crossing 0. 2 VDD to 0. 8 VDD q tf: fall time – From output crossing 0. 8 VDD to 0. 2 VDD 4: DC and Transient Response CMOS VLSI Design 40

Delay Definitions q tcdr: rising contamination delay – From input to rising output crossing VDD/2 q tcdf: falling contamination delay – From input to falling output crossing VDD/2 q tcd: average contamination delay – tpd = (tcdr + tcdf)/2 4: DC and Transient Response CMOS VLSI Design 41

Simulated Inverter Delay q Solving differential equations by hand is too hard q SPICE simulator solves the equations numerically – Uses more accurate I-V models too! q But simulations take time to write 4: DC and Transient Response CMOS VLSI Design 42

Delay Estimation q We would like to be able to easily estimate delay – Not as accurate as simulation – But easier to ask “What if? ” q The step response usually looks like a 1 st order RC response with a decaying exponential. q Use RC delay models to estimate delay – C = total capacitance on output node – Use effective resistance R – So that tpd = RC q Characterize transistors by finding their effective R – Depends on average current as gate switches 4: DC and Transient Response CMOS VLSI Design 43

RC Delay Models q Use equivalent circuits for MOS transistors – Ideal switch + capacitance and ON resistance – Unit n. MOS has resistance R, capacitance C – Unit p. MOS has resistance 2 R, capacitance C q Capacitance proportional to width q Resistance inversely proportional to width 4: DC and Transient Response CMOS VLSI Design 44

Example: 3 -input NAND q Sketch a 3 -input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R). 4: DC and Transient Response CMOS VLSI Design 45

Example: 3 -input NAND q Sketch a 3 -input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R). 4: DC and Transient Response CMOS VLSI Design 46

Example: 3 -input NAND q Sketch a 3 -input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R). 4: DC and Transient Response CMOS VLSI Design 47

3 -input NAND Caps q Annotate the 3 -input NAND gate with gate and diffusion capacitance. 4: DC and Transient Response CMOS VLSI Design 48

3 -input NAND Caps q Annotate the 3 -input NAND gate with gate and diffusion capacitance. 4: DC and Transient Response CMOS VLSI Design 49

3 -input NAND Caps q Annotate the 3 -input NAND gate with gate and diffusion capacitance. 4: DC and Transient Response CMOS VLSI Design 50

Elmore Delay q ON transistors look like resistors q Pullup or pulldown network modeled as RC ladder q Elmore delay of RC ladder 4: DC and Transient Response CMOS VLSI Design 51

Example: 2 -input NAND q Estimate worst-case rising and falling delay of 2 input NAND driving h identical gates. 4: DC and Transient Response CMOS VLSI Design 52

Example: 2 -input NAND q Estimate rising and falling propagation delays of a 2 input NAND driving h identical gates. 4: DC and Transient Response CMOS VLSI Design 53

Example: 2 -input NAND q Estimate rising and falling propagation delays of a 2 input NAND driving h identical gates. 4: DC and Transient Response CMOS VLSI Design 54

Example: 2 -input NAND q Estimate rising and falling propagation delays of a 2 input NAND driving h identical gates. 4: DC and Transient Response CMOS VLSI Design 55

Example: 2 -input NAND q Estimate rising and falling propagation delays of a 2 input NAND driving h identical gates. 4: DC and Transient Response CMOS VLSI Design 56

Example: 2 -input NAND q Estimate rising and falling propagation delays of a 2 input NAND driving h identical gates. 4: DC and Transient Response CMOS VLSI Design 57

Example: 2 -input NAND q Estimate rising and falling propagation delays of a 2 input NAND driving h identical gates. 4: DC and Transient Response CMOS VLSI Design 58

Delay Components q Delay has two parts – Parasitic delay • 6 or 7 RC • Independent of load – Effort delay • 4 h RC • Proportional to load capacitance 4: DC and Transient Response CMOS VLSI Design 59

Contamination Delay q Best-case (contamination) delay can be substantially less than propagation delay. q Ex: If both inputs fall simultaneously 4: DC and Transient Response CMOS VLSI Design 60

Diffusion Capacitance q we assumed contacted diffusion on every s / d. q Good layout minimizes diffusion area q Ex: NAND 3 layout shares one diffusion contact – Reduces output capacitance by 2 C – Merged uncontacted diffusion might help too 4: DC and Transient Response CMOS VLSI Design 61

Layout Comparison q Which layout is better? 4: DC and Transient Response CMOS VLSI Design 62