Standard Forms 2020113 Jackie Kan 2007 jackiekanLin Ton

Standard Forms 2020/11/3 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) NTU DSDhttp: //linton. 1 d 24 h. com/~jackiekan/ (Digital System Design) 2007 1

Some Terms n Product: The Logical AND, not Arithmetic Multiply Operation n Sum: The Logical OR , not Arithmetic Add Operation n Canonical Form (正規形式) p Min-terms (全及項的和) p Max-terms (全或項的積) n Standard Form (一般形式) p SOP - Sum of Products (積項和) p POS - Product of Sums (和項積) 2020/11/3 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 2

Min-term (全及項的和) Canonical Form (正規形式) n A product term (AND Term) in which all the variables appear exactly once, either complemented or uncomplemented, is called min-term. n There are 2 n distinct min-terms for n variables. X Y Z m 2 m 3 m 4 m 5 m 6 m 7 0 0 0 m 0 1 0 0 0 0 0 1 m 1 0 0 0 0 1 0 m 2 0 0 1 0 0 0 1 1 m 3 0 0 0 1 0 0 m 4 0 0 1 0 0 0 1 m 5 0 0 0 1 1 0 m 6 0 0 0 1 0 1 1 1 m 7 0 0 0 0 1 2020/11/3 Product Term Symbol m 0 m 1 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 3

Maxterm (全或項的積) Canonical Form (正規形式) n A sum term (OR Term) that contains all the variables in complemented or uncomplemented form is called a max-term. n There are 2 n distinct max-terms for n variables. X Y Z M 2 M 3 M 4 M 5 M 6 M 7 0 0 0 M 0 0 1 1 1 1 0 0 1 M 1 1 0 1 0 M 2 1 1 0 1 1 M 3 1 1 1 0 0 M 4 1 1 1 1 0 1 M 5 1 1 1 0 M 6 1 1 1 0 1 1 M 7 1 1 1 1 0 2020/11/3 Sum Term Symbol M 0 M 1 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 4

De. Morgan’s Laws n De. Morgan’s Laws provide an easy way to find the inverse of a Boolean expression: p (X + Y)’ = X’ Y’ p (XY)’ = X’ + Y’ n An easy way to remember this is that each TERM is complemented, and that ORs become ANDs; ANDs become ORs. n Easy to prove this via a truth table X 0 Y 0 0 1 1 1 0 1 1 2020/11/3 (X+Y)’ 0 1 X’Y’ 1 X 0 Y 0 XY 0 (XY)’ 1 X’+Y’ 1 0 0 0 1 1 1 0 0 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 5

Sum of Products (SOP/積項和) Expression n A sum of products expression is formed as follows. p Each row of the truth table in which the function takes on the value 1 contributes an ANDed term, using the asserted variable if there is a 1 in its column for that row or its complement if there is a 0. These are called minterms. p A min-term is defined as an ANDed product of literals in which each variable appears exactly once in either true or complemented form, but not both. p The min-terms are then ORed to form the expression for the function. The min-term expansion is unique because it is deterministically derived from the truth table. A 0 0 1 1 2020/11/3 B 0 0 1 1 C 0 1 0 1 F 0 0 0 1 1 1 F' 1 1 1 0 0 0 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 6

Sum of Products (SOP/積項和) Normal Form (一般形式) n A Boolean expression is in Sum Of Products form when all products are the products of single variables only p F = AB’ + CD’E + AC’E’ p G = ABC’ + DEFG + H p H = AA’ + ABC’ p Y = A + B’ + C + D p Z = (A+B)CD + EF = ACD + BCD + EF 2020/11/3 SOP Form Not SOP Form, Non-Standard Form SOP Form Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 7

Product of Sums (POS/和項積) Expression n A product of sums expression is formed as follows. p Each row of the truth table in which the function takes on the value 0 contributes an ORed term, using the complemented variable if there is a 0 in its column for that row or its complement if there is a 1. These are called max -terms. p A max-term is defined as an ORed product of literals in which each variable appears exactly once in either true or complemented form, but not both. p The max-terms are then ANDed to form the expression for the function. The max-term expansion is unique because it is deterministically derived from the truth table. A 0 0 1 1 2020/11/3 B 0 0 1 1 C 0 1 0 1 F 0 0 0 1 1 1 F' 1 1 1 0 0 0 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 8

Product of Sums (POS/和項積) Normal Form (一般形式) n A Boolean expression is in Product Of Sums form when all sums are the sums of single variables p F = (A + B’)(C + D’ + E)(A + C’ + E’) p G = A (B + E)(C + D) p Y = AB + AC = (A)(B + C) 2020/11/3 POS Form Not POS Form, SOP Form POS Form Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 9

Decimal Notation n Sum of Min-terms p F(A, B, C) = Σm(0, 4, 5) = m 0 + m 4 + m 5 = A'B'C' + AB'C n Product of Max-terms p F(A, B, C) = ΠM(1, 2, 3, 6, 7) = (M 1)(M 2)(M 3)(M 6)(M 7) = (A+B+C')(A'+B+C')(A+B’+C’)(A’+B’+C’) n For an n Variables Function p Number of Min-terms + Number of Max-terms = 2 n (2的n次方個) 2020/11/3 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 10

SOP Canonical/Standard and Minimal Form A B C Maxterm Symbol 0 0 0 A’B’C’ m 0 0 0 1 A’B’C m 1 0 A’BC’ m 2 0 1 1 A’BC m 3 1 0 0 AB’C’ m 4 1 0 1 AB’C m 5 1 1 0 ABC’ m 6 1 1 1 ABC m 7 2020/11/3 F in CSOP canonical (SOP標準式/Standard) form : F(A, B, C) = ∑m(1, 3, 5, 6, 7) = m 1 + m 3 + m 5 + m 6 + m 7 = A'B'C + A'BC + AB'C + ABC' + ABC canonical form (正規式) minimal form (最簡式) F(A, B, C) = = = A'B'C + A'BC + AB'C + ABC' (A'B' + A'B + AB' + AB)C + ABC' ((A' + A)(B' + B))C + ABC' + C AB + C (最簡式) Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 11

POS Canonical/Standard and Minimal Form A B C Minterm 0 0 0 A+B+C 0 0 1 A+B+C’ 0 1 0 A+B’+C M 2 0 1 1 A+B’+C’ M 3 1 0 0 A’+B+C M 4 1 0 1 A’+B+C’ M 5 1 1 0 A’+B’+C M 6 1 1 1 A’+B’+C’ M 7 2020/11/3 Symbol F in CPOS canonical (POS標準式/Standard) Form: F(A, B, C) = ΠM(0, 2, 4) M 0 = M 0 • M 2 • M 4 = (A+B+C) (A+B'+C) (A'+B+C) M 1 canonical form (正規式) minimal form (最簡式) F(A, B, C) = (A+B+C) (A+B'+C) (A'+B+C) = (A + B + C) (A + B' + C) (A + B + C) (A' + B + C) = (A + C) (B + C) (最簡式) Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 12

Summary n Sum of Products (SOP): AND-of-Ors / Product of Sums (POS): OR-of-ANDs n Canonical Sum of Products / Product of Sums (CSOP/CPOS) 正規式 p Any Boolean function that is expressed as a sum of min-terms, or as a product of max-terms is said to be in its canonical form. p F = x' y z + x y' z + x y z' + x y z p F' = (x+y'+z') • (x'+y'+z) • (x'+y'+z') n Normal Sum of Products/Product of Sums (NSOP/NSOP) 一般式 p A Boolean function is said to be in a normal form if a sum-of-products expression or a product-of-sums expression has at least one term that is not a min-term or a max-terms respectively. p F = xy'z + xyz' + yz n Non-Standard Form or Non-Normal Form 非一般式 p common variables in a normal form expression can be factored out. The resulting expression is no longer in a sum-of-products or product-of-sums format. These expressions are in a non-standard form or non-normal form. p F = x(y'z + yz') + yz n Minimal Form 最簡式 p Need simplified the expression 2020/11/3 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 13

Quiz 1 n Please complete the follows table AB'+A'C+B'C (A+B')(A'+B+C)(A+B+C) A'B'C+A'B'C' A'B+AB'C'+A'C (A'+B+C')(A+B'+C')(A+B+C) (A'+B)(A+B'+C')(A'+B'+C) 2020/11/3 NSOP V NPOS V V CSOP CPOS V V V Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 14

NAND & NOR Gates 2020/11/3 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) NTU DSDhttp: //linton. 1 d 24 h. com/~jackiekan/ (Digital System Design) 2007 15

NAND, NOR Gates n Why do we care about De. Morgan’s Law? n There are two other gate types that produce the complement of a boolean function! A 0 0 1 1 A B 2020/11/3 B 0 1 Y 1 1 1 0 A 0 0 1 1 Y=(AB)’ A B 0 1 Y 1 0 0 0 Y=(A+B)’ B Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 16

NAND, NOR n NAND (NOT AND) p Can be thought of as an AND gate followed by an inverter A Y=(AB)’ A B B Y=(AB)’ AB n NOR (NOT OR) p Can be thought as an OR gate followed by an inverter A B 2020/11/3 Y=(A+B)’ A B Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ Y=(A+B)’ A+B 17

Actually …. n In the real world p An AND gate is made from a NAND gate followed by an inverter p An OR gate is made from a NOR gate followed by an inverter 2020/11/3 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 18

MOS Transistor n MOS transistors have three terminals: drain, gate, and source p They act as switches as follows: u if voltage on gate terminal is (some amount) higher/lower than source terminal then a conducting path is established between drain and source terminals G G S D N-channel open when voltage at G is low closes when: voltage(G) > voltage (S) + 2020/11/3 S D P-channel closed when voltage at G is low opens when: voltage(G) < voltage (S) – Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 19

MOS Network n X 與 Y 的關係為何 X Y 0 V 3 V 3 V 0 V G N-MOS G = 0, S-D Off / G = 1, On S G D P-MOS G = 0, S-D On / G = 1, Off S 2020/11/3 D Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 20

Using CMOS Implement AND Gate G N-MOS G = 0, S-D Off / G = 1, On S D G P-MOS G = 0, S-D On / G = 1, Off S 2020/11/3 D x y S 1 S 2 S 3 S 4 S 5 S 6 z 0 0 off on on off on 0 0 1 on off off on 0 1 0 off on 0 1 1 on on off 1 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 21

Using CMOS Implement OR Gate G N-MOS G = 0, S-D Off / G = 1, On S D G P-MOS G = 0, S-D On / G = 1, Off S 2020/11/3 D x y S 1 S 2 S 3 S 4 S 5 S 6 z 0 0 off on on off on 0 0 1 off on on off 1 1 0 on off 1 1 1 on on off 1 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 22

Using CMOS Implement NAND / NOR Gate S 1 S 3 S 2 S 1 S 4 S 3 x y S 1 S 2 S 3 S 4 z 0 0 on on off off 1 0 1 on off on 0 1 0 off on on off 1 1 0 off on on off 0 1 1 off off on on 0 2020/11/3 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 23

CMOS – AND 與 NAND S 2 S 1 S 4 S 3 n Propogation Delay 傳輸延遲 p AND - 2, NAND - 1 n MOS電晶體數 p AND – 6個, NAND – 4個 2020/11/3 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 24

CMOS – OR 與 NOR S 1 S 3 S 2 S 4 n Propogation Delay 傳輸延遲 p OR - 2, NOR - 1 n MOS電晶體數 p OR – 6個, NOR – 4個 2020/11/3 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 25

NAND-NAND Form = AND-OR Form A (AB)’ F = ((AB)’ (CD)’)’ B C D A (CD)’ Same Logic Function AB F = AB+CD B C D 2020/11/3 CD Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 26

NOR-NOR Form = OR-AND Form A (A+B)’ F = ((A+B)’ (C+D)’)’ B C D A (C+D)’ Same Logic Function A+B F = (A+B)(C+D) B C D 2020/11/3 C+D Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 27

Summary 2020/11/3 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 28

Summary 2020/11/3 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 29

SOP and POS Examples jackiekan@solutioninside. com 2020/11/3 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) NTU DSDhttp: //linton. 1 d 24 h. com/~jackiekan/ (Digital System Design) 2007 30

SOP & POS F = ∑m(1, 3, 5, 7) = A’B’C+A’BC+AB’C+ABC F’ = ΠM(0, 2, 4, 6) = (A+B+C)(A+B’+C) (A’+B+C)(A’+B’+C) F’ = ∑m(0, 2, 4, 6) = A’B’C’+A’BC’+AB’C’+ABC’ F = (A’B’C’+A’BC’+AB’C’+ABC’)’ = (A’B’C’)’(A’BC’)’(AB’C’)’(ABC’)’ = (A+B+C)(A+B’+C) (A’+B+C)(A’+B’+C) 2020/11/3 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 31

Simulation Program (Verilog Code) n F(A, B, C, D) = ∑m(3, 4, 5, 6, 7, 11, 14) module myf 1(f, a, b, c, d); output f; input a, b, c, d; //MAX (0, 1, 2, 8, 9, 10, 12, 13, 15) assign f = ((a|b|c|d) & (a|b|c|!d) & (a|b|!c|d) & (!a|b|c|!d) & (!a|b|!c|d) & (!a|!b|c|d)& (!a|!b|c|!d) & (!a|!b|!c|!d)); endmodule myf 2(f, a, b, c, d); output f; input a, b, c, d; //MIN (3, 4, 5, 6, 7, 11, 14) assign f = ((!a&!b&c&d) | (!a&b&!c&!d) | (!a&b&!c&d) | (!a&b&c&!d) | (!a&b&c&d) | (a&!b&c&d) | (a&b&c&!d) ); endmodule 2020/11/3 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 32

Simulation Results 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 f 1=MAX(0, 1, 2, 8, 9, 10, 12, 13, 15) f 2=MIN (3, 4, 5, 6, 7, 11, 14) 2020/11/3 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 33

Quiz 2) Please draw the AND-OR form and OR-AND form circuits of F 1 & F 2. F 1 = MIN (3, 5, 6, 7, 11) F 2’ = Σm (2, 7, 13, 14, 15) 3) Draw the Truth Table, Minterm and Maxterm, and ALL-NAND Circuit of F 3 & ALL-NOR Circuit of F 4. F 3 = A’BC+AB’CD’+ABC’+A’B’CD F 4’ = AB + CB + D’E Note: All gates must be only 2 -inputs and 1 -output in Quiz 3. 2020/11/3 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 34

Enable and Inhibit Properties of Logic Gates 2020/11/3 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) NTU DSDhttp: //linton. 1 d 24 h. com/~jackiekan/ (Digital System Design) 2007 35

AND Gate A Y B A B Y Gate Inhibited 2020/11/3 Gate Enabled Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 36

OR Gate A Y B A B Y Gate Enabled 2020/11/3 Gate Inhibited Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 37

NAND Gate A Y B A B Y Gate Inhibited 2020/11/3 Gate Enabled Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 38

NOR Gate A Y B A B Y Gate Enabled 2020/11/3 Gate Inhibited Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 39

XOR Gate A Y B A B Y Gate Enabled (True) 2020/11/3 Gate Inhibited (Complement) Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 40

Summary of Enable/Inhibit Properties Control AND A=0 Y=0 A=1 Y=B 2020/11/3 OR NAND NOR Y=B Y=1 Y=B’ Y=0 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ XOR XNOR Y=B’ Y=B 41

IC Family 2020/11/3 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) NTU DSDhttp: //linton. 1 d 24 h. com/~jackiekan/ (Digital System Design) 2007 42

Family Characteristics n TTL p Transistor-based p Faster than CMOS p Larger current carrying capability p Higher power consumption p High voltage requirements n CMOS p MOSFET-based p Greater noise immunity p Low power consumption p Variable voltage requirements p Low speed 2020/11/3 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 43

Transistor ON & OFF n 飽和區(ON) n 截止區(OFF) B-E順向偏壓且 有足夠大的IB 2020/11/3 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ B-E沒有偏壓或 逆向偏壓 44

TTL IC Characteristics n 基本電路(ex. NOT Gate) = 輸入層 2020/11/3 驅動層 輸出層 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 45

TTL IC Characteristics n 當輸入為HI, 則輸出為LO n 當輸入為LO, 則輸出為HI 2020/11/3 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 46

TTL NAND A B 0 0 0 1 1 2020/11/3 ICQ 1 + + + - Q 1 ON ON ON OFF Q 2 OFF OFF ON Q 3 OFF OFF ON Q 4 Y O/P ON 1 OFF 0 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 47

Propagation Delay Definitions 2020/11/3 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 48

Propagation Delay CMOS measured at 50% mark 2020/11/3 TTL measured at 1. 5 Volt mark Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 49

Propagation Delay n Propagation Delay in a circuit is the sum of all the propagation delays in the output path n Always use the worst-case when designing. 2020/11/3 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 50

Example n Determine the propagation delay for the following circuit, assuming p Tp. LH: 11 n. S typical, 22 n. S maximum p Tp. HL: 7 n. S typical, 15 n. S maximum. n Total Delay • Tp. LH + Tp. HL + Tp. LH = 22 n. S + 15 n. S + 22 n. S = 59 n. S • Tp. HL + Tp. LH + Tp. HL= 15 n. S + 22 n. S + 15 n. S = 52 n. S • Total Propagation Delay is 59 n. S 2020/11/3 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 51

Source and Sink Output sinks current in a low state Output sources current in a high state 2020/11/3 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 52

Driving and Loading n Driving gate p A gate providing a logic level to other gates n Loading gate p A gate that receives a logic level from other gates 2020/11/3 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 53

Input and Output Current n IIL: Input Low Current p Current measured when input is in a low state n IIH: Input High Current p Current measured when input is in a high state n IOL: Output Low Current p Current measured when output is in a low state n IOH: Output High Current p Current measured when output is in a high state 2020/11/3 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 54

Fanout & Fanout Calculation n Fanout is the number of load inputs that a driving gate is capable of handling. How many loading inputs are present? n Must calculate for BOTH output high and output low. Select the worstcase condition. n Consider the TTL 7404: Worst-case = 10 2020/11/3 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 55

Logic Minimization Tool - Boolean Cubes Jackie Kan jackiekan@solutioninside. com 2020/11/3 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) NTU DSDhttp: //linton. 1 d 24 h. com/~jackiekan/ (Digital System Design) 2007 56

The Uniting Theorem (1/2) n Key tool to simplification: p A (B' + B) = A n 簡化 Two-Level Logic (MIN Term) n Find two element subsets of the ON-set where only one variable changes its value p this single varying variable can be eliminated and a single product term used to represent both elements 2020/11/3 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 57

The Uniting Theorem (2/2) n F = A'B'+AB' = (A'+A)B' = B' Ü 相鄰定理 (Adjacency Theorem) XY + XY' = X (X + Y)(X + Y') = X 2020/11/3 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 58

Boolean Cubes (1/2) n Visual technique for identifying when the uniting theorem can be applied n n 個輸入變數 = n-dimensional "cube" 2020/11/3 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 59

Mapping Truth Tables into Boolean Cubes 上 (1/2) n ON-Set p Output 為 1 n OFF-Set p Output 為 0 n DC-Set (Don’t Care) p Output 為 0 或 Output 為 1 都沒有關係 n Face p Boolean Cube 的 Sub-Cube 2020/11/3 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 60

Mapping Truth Tables into Boolean Cubes 上 (2/2) n Uniting theorem 合成 two “faces” of a cube 成為 a larger "face" n Example two faces of size 0 (Nodes) combine into a face of size 1(Line) F 11 01 B 00 A 10 1 : ON-Set : AB = 00, 10 0 : OFF-Set : AB = 01, 11 X : DC-Set : Don’t Care 2020/11/3 ON-Set : A’B’ & AB’ Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 61

使用Boolean Cubes來化簡 (1/3) F n A 變數不變 n B 變數改變 n AB’ + AB = A G n B 變數的補數不變 n A 變數改變 n A’B’ + AB’ = B’ Ü求SOP最簡式 由所能形成之最大的Face先找起 涵蓋所有的ON-Set 2020/11/3 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 62

使用Boolean Cubes來化簡 (2/3) n 三個變數範例: Full Adder’s Carry Out A B (Cin' + Cin) A B Cin Cout 0 0 0 1 1 0 0 0 1 1 1 1 0 1 1 1 (A' + A) B Cin 011 111 010 110 B 001 101 Cin 000 A Cout = B Cin + A B 2020/11/3 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 100 A (B + B') Cin 63

使用Boolean Cubes來化簡 (3/3) n Face Size超過 2 的化簡 p F(A, B, C) = m(4, 5, 6, 7) n F(W, X, Y, Z) = m(0, 2, 3, 5, 6, 7, 8, 10, 11, 14, 15) 2020/11/3 Jackie Kan - 2007 (jackiekan@Lin. Ton. 1 D 24 H. com/jackiekan@csie. ntu. edu. tw) http: //linton. 1 d 24 h. com/~jackiekan/ 64