Microprocessors Parviz Keshavarzi Intel X 86 Microprocessors 1

Microprocessors Parviz Keshavarzi Intel X 86 Microprocessors (1) Sept. 2012

The First Computer Microprocessors Semnan University 2 Intel X 86 Micros 2

ENIAC - The first electronic computer (1946) Microprocessors Semnan University 3 Intel X 86 Micros 3

The Transistor Revolution First transistor Bell Labs, 1948 Microprocessors Semnan University 4 Intel X 86 Micros 4

The First Integrated Circuits Bipolar logic 1960’s ECL 3 -input Gate Motorola 1966 Microprocessors Semnan University 5 Intel X 86 Micros 5

Intel 4004 Micro-Processor 1971 1000 transistors 1 MHz operation Microprocessors Semnan University 6 Intel X 86 Micros 6

Intel Pentium (IV) microprocessor Microprocessors Semnan University 7 Intel X 86 Micros 7

Moore’s Law l. In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. l. He made a prediction that semiconductor technology will double its effectiveness every 18 months Microprocessors Semnan University 8 Intel X 86 Micros 8

Moore’s Law Electronics, April 19, 1965. Microprocessors Semnan University 9 Intel X 86 Micros 9

Evolution in Complexity Microprocessors Semnan University 10 Intel X 86 Micros 10

Transistor Counts 1, 000 1 Billion Transistors K 100, 000 1, 000 10 Pentium® ® Pentium III ® Pro Pentium II Pentium® i 486 i 386 80286 8086 Source: Intel 1 1975 1980 1985 1990 1995 2000 2005 2010 Projected Microprocessors Semnan University Courtesy, Intel 11 Intel X 86 Micros 11

Moore’s law in Microprocessors Transistors (MT) 1000 10 1 2 X growth in 1. 96 years! P 6 Pentium® proc 486 386 0. 1 286 8085 Transistors on Lead Microprocessors double every 2 years 0. 01 8080 8008 4004 0. 001 1970 1980 1990 2000 2010 Year Microprocessors Semnan University Courtesy, Intel 12 Intel X 86 Micros 12

Die Size Growth Die size (mm) 100 P 6 Pentium ® proc 486 10 386 286 8080 8086 ~7% growth per year 8085 8008 ~2 X growth in 10 years 4004 1 1970 1980 1990 Year 2000 2010 Die size grows by 14% to satisfy Moore’s Law Microprocessors Semnan University Courtesy, Intel 13 Intel X 86 Micros 13

Frequency (Mhz) 10000 Doubles every 2 years 1000 10 1 8085 8086 286 386 P 6 Pentium ® proc 486 8080 8008 4004 0. 1 1970 1980 1990 Year 2000 2010 Lead Microprocessors frequency doubles every 2 years Microprocessors Semnan University Courtesy, Intel 14 Intel X 86 Micros 14

Power Dissipation Power (Watts) 100 P 6 Pentium ® proc 10 8086 286 1 8085 8080 8008 4004 486 386 0. 1 1974 1978 1985 Year 1992 2000 Lead Microprocessors power continues to increase Microprocessors Semnan University Courtesy, Intel 15 Intel X 86 Micros 15

Power will be a major problem Power (Watts) 100000 18 KW 5 KW 1. 5 KW 500 W 10000 100 Pentium® proc 286 486 8086 10 386 8085 8080 8008 1 4004 0. 1 1974 1978 1985 1992 2000 2004 2008 Year Power delivery and dissipation will be prohibitive Microprocessors Semnan University Courtesy, Intel 16 Intel X 86 Micros 16

Power density Power Density (W/cm 2) 10000 100 Rocket Nozzle Nuclear Reactor 8086 10 4004 Hot Plate P 6 8008 8085 Pentium® proc 386 286 486 8080 1 1970 1980 1990 2000 2010 Year Power density too high to keep junctions at low temp Microprocessors Semnan University Courtesy, Intel 17 Intel X 86 Micros 17

Intel 8086/8088 Microprocessors q Intel 8086 and 8088 Microprocessors are the basis of all IBM-PC compatible computers (8086 introduced in 1978, first IBM-PC released in 1981) All Intel, AMD and other advanced microprocessors are based on and are compatible with the original 8086/8 q At Power Up and Reset time, Pentiums, Athlons etc all look like 8086 processors q Microprocessors Semnan University Intel X 86 Micros 18

Intel 8086/8088 Microprocessors Intel 8086 is a 16 -bit microprocessor q 16 -bit data registers q 16 or 8 bit external data bus q Some techniques to optimise the CPU performance when it’s executing programs q Segment: Offset memory model q Little-Endian Data Format q Microprocessors Semnan University Intel X 86 Micros 19

8086/8088 (1) Original IBM PC used 8088 micrprocessor q 8088 is similar to the 8086 microprocessor but it has an external 8 -bit bus & only 4 -deep queue q § For cost reduction reasons We can consider 8086 and 8088 together q PC clones often used 8086 for better performance q 8 -bit bus reduces performance, but meant cheaper computers q Microprocessors Semnan University Intel X 86 Micros 20

8086/8088 (2) Remember the Fetch-Decode-Execute cycle? q Fetching from EXTERNAL MEMORY is SLOW q The 8086/8 used an instruction queue to speed up performance q While the processor is decoding and executing an instruction, its bus interface can be reading new instructions, since at that time the bus is not actually in use q Microprocessors Semnan University Intel X 86 Micros 21

8086/8088 Functional Units Microprocessors Semnan University Intel X 86 Micros 22

8086/8088 (3) q 8086/8088 consists of two internal units § The execution unit (EU) - executes the instructions § The bus interface unit (BIU) - fetches instructions, reads operands and writes results The 8086 has a 6 -byte prefetch queue q The 8088 has a 4 -byte prefetch queue q Microprocessors Semnan University Intel X 86 Micros 23

8086/8088 Internal Organisation Microprocessors Semnan University Intel X 86 Micros 24

BIU Elements q Instruction Queue: the next instructions or data can be fetched from memory while the processor is executing the current instruction § The memory interface is slower than the processor execution time so this speeds up overall performance q Segment Registers: § CS, DS, SS and ES are 16 -bit registers § Used with the 16 -bit Base registers to generate the 20 -bit address § Allow the 8086/8088 to address 1 Mb of memory § Changed under program control to point to different segments as a program executes q Instruction Pointer (IP) contains the Offset Address of the next instruction, the distance in bytes from the address given by the current CS register Microprocessors Semnan University Intel X 86 Micros 25

8086/8088 20 -bit Addresses Microprocessors Semnan University Intel X 86 Micros 26

Exercise: 20 -bit Addressing 1. 2. CS contains 0 A 820 h, IP contains 0 CE 24 h. What is the resulting physical address? CS contains 0 B 500 h, IP contains 0024 h. What is the resulting physical address? Microprocessors Semnan University Intel X 86 Micros 27

8086/8 In Circuit (1) 8086/8 microprocessors need support circuits in a microcomputer system q 8086/8 multiplex the address and data buses on the same pins q This saves pins but at a price: q § Demultiplexing logic is needed to build up separate address and data buses to interface with RAMs and ROMs Microprocessors Semnan University Intel X 86 Micros 28

Microprocessors Semnan University Intel X 86 Micros 29

Microprocessors Semnan University Intel X 86 Micros 30

8086/8 In Circuit (2) In Maximum Mode the 8086/8 needs at least the following: 8288 Bus Controller, 8284 A Clock Generator, 74 HC 373 s and 74 HC 245 s q With the aid of these devices the 8086 begins to look like the ideal microprocessor we looked at earlier q Microprocessors Semnan University Intel X 86 Micros 31

Microprocessors Semnan University Intel X 86 Micros 32

8086/8 Maximum Mode q In maximum mode, the 8288 uses a set of status signals (S 0, S 1, S 2) to rebuild the normal bus control signals of the microprocessor § MRDC#, MWTC#, IORC#, IOWC# etc § Equivalent to MEMR# etc q Look at some special signals briefly Microprocessors Semnan University Intel X 86 Micros 33

RESET# Signal q q q The Active low RESET# signal puts the 8086/8 into a defined state Clears the flags register, segment registers etc. Sets the effective program address to 0 FFFF 0 h (CS=0 F 000 h, IP=0 FFF 0 h) 8086/8 Programs always start at FFFF 0 H after Reset has been asserted and removed Continues into latest generation CPUs Microprocessors Semnan University Intel X 86 Micros 34

BHE# Signal (8086 Only) The 8086 processor can address memory a byte at a time q Its data bus is 16 -bits wide q It uses the BHE# signal and A 0 (sometimes called BLE#) to address bytes using its 16 -bit bus q Microprocessors Semnan University Intel X 86 Micros 35

Use of BHE#/A 0(BLE#) Microprocessors Semnan University Intel X 86 Micros 36

Use of BHE#/BLE# BHE# A 0/BLE# 0 0 Whole word (16 -bits) 0 1 High byte to/from odd address 1 0 Low byte to/from even address 1 1 No selection Microprocessors Selection Semnan University Intel X 86 Micros 37

ALE and Address/data Bus Multiplexing 8086/8 Multiplexes the Address and Data signals onto the same set of pins q Need off-chip logic to separate the signals q Transparent latches designed just for address demultiplexing q Microprocessors Semnan University Intel X 86 Micros 38

ALE and 74 HC 373 Transparent Latch Microprocessors Semnan University Intel X 86 Micros 39

Use of ALE (Address Latch Enable) ALE is used with an external latch (74 HC 373) to demultiplex the address and data lines q 74 HC 373 is transparent when its LE input (connected to ALE) is high q When ALE goes low, the ‘ 373 holds the last data until ALE goes high again q Microprocessors Semnan University Intel X 86 Micros 40

8288 Bus Controller and Bus Transceivers Microprocessors Semnan University Intel X 86 Micros 41

8086 Read Cycle Microprocessors Semnan University Intel X 86 Micros 42

8086 Write Cycle Microprocessors Semnan University Intel X 86 Micros 43

8086 Read Cycle (1 Wait State) Microprocessors Semnan University Intel X 86 Micros 44

8086/8088 Summary First Generation (introduced June 1978) q One of the first 16 -bit processors on the market q 16 -bit internal registers q 16/8 -bit external data bus q 20 -bit address bus (1 MB addressable) q Used in 1 st generation IBM PCs (1981) q Microprocessors Semnan University Intel X 86 Micros 45

80186/80188 Evolution of 8086/8088 80186/80188 q Increased instruction set q On-chip system components (Clock generator, DMA, Interrupt, Timers…) q Unsuccessful in PCs q Popular in embedded systems… q Microprocessors Semnan University Intel X 86 Micros 46

2 nd Generation Processor 286 q q q q P 2 (286) = 2 nd Generation Processor Introduced in 1981 CPU behind IBM AT Throughput of original IBM AT (6 MHz) was about 500% of IBM PC (4. 77 MHz) Level of integration: 134 k transistors (vs 29 k in 8086) Still a 16 -bit processor… Available in higher clock frequencies: 25 MHz Microprocessors Semnan University Intel X 86 Micros 47

2 nd Generation Processors 286 q Fully backwards compatible to 8086 80286 runs 8086 software without modification q Improved instruction execution Average instruction takes 4. 5 cycles vs. 12 cycles (8086) q q Improved instruction set Real mode and Protected Mode Multitasking-support. What happens in one area of memory doesn’t affect other programs. Protected mode supported by Windows 3. 0. q q q 16 MB addressable physical memory On-chip MMU (1 GB virtual memory) Non-multiplexed address-bus and data-bus Microprocessors Semnan University Intel X 86 Micros 48

Improving Computer Performance We’ve seen how 16 -bit computer technology based on the 8086 and 80286 processors developed q These computers are not powerful enough for today’s applications q How do you improve the performance of your computer? q Let’s start with the CPU q Microprocessors Semnan University Intel X 86 Micros 49

CPU Performance (1) MOST OBVIOUS: Processor Clock Frequency q Increased frequency – increased execution rate q State of the Art: >2 GHz (Jan 2002) q Memory and I/O access times can be performance bottleneck – unless you take some special measures q Microprocessors Semnan University Intel X 86 Micros 50

CPU Performance (2) q ALU register width § A processor is an n-bit processor, where N represents the precision of the ALU – N can be 4, 8, 16, 32, or 64 § The wider the registers – the more processing per clock q Data bus width § The wider the data bus the faster we can transfer data § Since the memory and I/O device access times are finite, the more bits transferred per cycle the better Microprocessors Semnan University Intel X 86 Micros 51

CPU Performance (3) q q q Address bus width Increased address width doesn’t provide a ‘speed’ increase as such CPU can directly address more memory PCs use big programs, which would not fit in a smaller address space Overcoming small address space takes time § Impacts on overall system performance Microprocessors Semnan University Intel X 86 Micros 52

3 rd Generation Processor 386 q q q P 3 (386) = 3 rd Generation Processor Introduced: 10/1985 Full 32 -bit processor (32 -bit registers. 32 -bit internal and external databus. 32 -bit address bus) q 275 k transistors. CMOS. 132 -pin PGA package. (Supply current Icc=400 m. A. Roughly the same as 8086 !) q q Clock speeds: 16 -33 MHz P 3 processors were far ahead of their time: It took 10 years before 32 -bit operating systems became mainstream! q First 386 PCs early 1987 (COMPAQ) Microprocessors Semnan University Intel X 86 Micros 53

3 rd Generation Processor 386 q Modes of operation: § Real. Protected. Virtual Real. q Protected mode of 386 is fully compatible with 286 Protected mode=native mode of operation. Chips are designed for advanced operating systems such as Windows NT q New virtual real mode Processor can run with hardware memory protection while simulating the 8086’s real-mode operation. Multiple copies of e. g. DOS can run simultaneously, each in a protected area of memory. If a program in one memory area crashes, the rest of the system is protected. Microprocessors Semnan University Intel X 86 Micros 54

Intel 32 -bit Architecture: IA-32 Microprocessors Semnan University Intel X 86 Micros 55

80386 Features q q q q 32 -bit general and offset registers 16 -byte prefetch queue Memory management unit with segmentation unit and paging unit 32 -bit address and data bus 4 -Gbyte physical address space 64 -Tbyte virtual address space i 387 numerical coprocessor Implementation of real, protected and virtual 8086 modes Microprocessors Semnan University Intel X 86 Micros 56

80386 Operating Modes q q Protected Mode for Multitasking support Real Mode (native 8086 mode) § Processor powers up in Real Mode q System Management Mode § Power management or system security § Processor switches to separate address space, while saving the entire context of the currently running program or task Microprocessors Semnan University Intel X 86 Micros 57

80386 Register Set Microprocessors Semnan University Intel X 86 Micros 58

80386 Prefetch Queue Fetching from on-chip Queue is fast Microprocessors Reading from off-chip Memory is slow Semnan University Intel X 86 Micros 59

80386 Prefetch Queue q 1. 2. 80386 Prefetch queue is 16 -bytes deep The instruction fetch can read from the prefetch queue faster than from memory The prefetcher can do some work while the execution unit is doing other tasks in parallel Microprocessors Semnan University Intel X 86 Micros 60

Coprocessor: i 387 The hardware implementation of floating point processing in the i 387 means floating point operations run at much higher speed. q The i 386 can execute all mathematical expressions using software emulation of the i 387. q Microprocessors Semnan University Intel X 86 Micros 61

80386: Classic CISC Processor CISC = Complex Instruction Set Computer q Complex instructions q. . . but code-size efficient q Micro-encoding of the machine instructions q Extensive addressing capabilities for memory operations q Few, but very useful CPU registers q Microprocessors Semnan University Intel X 86 Micros 62

80386 Execution Sequence Microprocessors Semnan University Intel X 86 Micros 63

80386 Complex Instructions CISC drawback: Most instructions are so complicated, they have to be broken into a sequence of micro-steps q These steps are called Micro-Code q Stored in a ROM in the processor core q Micro-code ROM: Access-time and size. . . q They require extra ROM and decode logic q Microprocessors Semnan University Intel X 86 Micros 64

RISC: Less is More RISC = Reduced Instruction Set Computer q 20/80 Rule: 20% of the instructions take up 80% of the time q Sometimes executing a sequence of simple instructions runs quicker than a single complex machine instruction that has the same effect q Microprocessors Semnan University Intel X 86 Micros 65

RISC Ideas (1) q Reduce the instruction set to simplify the decoding § Smaller Instruction Set -> Simpler Logic -> Smaller Logic -> Faster Execution Eliminate microcode – hardwire all instruction execution q Pipeline instruction decoding and executing – do more operations in parallel q Microprocessors Semnan University Intel X 86 Micros 66

RISC Ideas (2) q Load/Store Architecture – only the load and store instructions can access memory § All other instructions work with the processor internal registers § This is necessary for single-cycle execution – the execution unit can’t wait for data to be read/written Microprocessors Semnan University Intel X 86 Micros 67

RISC Ideas (3) q q q Increase number of internal register due to Load/Store Architecture Also registers are more general purpose and less associated with specific functions Compiler designed along with the RISC processor deesign. Compiler has to be aware of the processor architecture to produce code that can be executed efficiently Microprocessors Semnan University Intel X 86 Micros 68

Instruction Pipelining - Operations Can Be Carried Out in Parallel Read the instruction from memory or the prefetch queue (instruction fetch phase) q Decode the instruction (decode phase) q Where necessary, fetch the operands (operand fetch phase) q Execute the instruction (execute phase) q Write back the result (write-back phase) q Microprocessors Semnan University Intel X 86 Micros 69

Pipelined Execution Microprocessors Semnan University Intel X 86 Micros 70

Superscalar Architecture: The processor may have more than one pipeline (Pentium…) q Where possible each pipeline works independently q § Not always possible q May achieve average completed execution of more than one instruction per clock cycle Microprocessors Semnan University Intel X 86 Micros 71

Pipelining problems q More logic per pipeline stage – same resource can’t be used twice § E. g. can’t re-use ALU for computing implied addresses Synchronisation Problems q Delayed Jump/Branch q Data and Register dependency, e. g. q ADD reg 1, reg 2, reg 7 AND reg 6, reg 1, reg 3 Microprocessors Semnan University Intel X 86 Micros 72

Getting the Benefits of Pipelining q q Simplified Instruction decoding § Simpler, faster logic On-chip cache memories § Local memory on-chip to avoid memory access bottlenecks Floating Point pipeline for FP coprocessor Speculative Execution to get around pipeline flushes Microprocessors Semnan University Intel X 86 Micros 73

Software Implications of RISCs q Optimising Compiler must know how pipeline works (Compiler must be aware of pipeline delays, and insert NOPs if need be) q Lower code density in RISC because instructions are less efficient § Power. PC code takes up to 30% more code to do the same tasks as an x 86 CPU § more memory accesses, potential performance impact. . . Microprocessors Semnan University Intel X 86 Micros 74

80486: IA-32 with RISC elements q q q q q Introduced 04/91 Greatly improved 80386 CPU Hard-wired implementation of frequently used instructions (as in RISCs). On average 2 clock cycles/instruction. 5 stage instruction pipeline Internal L 1 Cache Memory (8 k. B) + cache controller On-chip Floating Point coprocessor (FPU) Longer Prefetch Queue (32 -bytes as opposed to 16 on the 80386) Higher frequency operation: up to 120 MHz >1. 2 M transistors, 0. 8 mm CMOS. 168 -pin PGA. Microprocessors Semnan University Intel X 86 Micros 75

80486 Block Diagram Microprocessors Semnan University Intel X 86 Micros 76

80486 Pipeline Microprocessors Semnan University Intel X 86 Micros 77