ARM Microprocessors Content q The ARM processor q

ARM Microprocessors

Content q. The ARM processor q. ARM instruction set q. Summary

The ARM processor 3

ARM Ltd q ARM was originally developed at Acron Computer Limited, of Cambridge, England between 1983 and 1985. – 1980, RISC concept at Stanford and Berkeley universities. – First RISC processor for commercial use q 1990 Nov, ARM Ltd was founded q ARM cores – Licensed to partners who fabricate and sell to customers. q Technologies assist to design in the ARM application – Software tools, boards, debug hardware, application software, bus architectures, peripherals etc… q Modification of the acronym expansion to Advanced RISC Machine. 4

ARM Ltd Design and license ARM core design but not fabricate

Why ARM? q One of the most licensed and thus widespread processor cores in the world – Used in PDA, cell phones, multimedia players, handheld game console, digital TV and cameras q Used especially in portable devices due to its low power consumption and reasonable performance

ARM processors q A simple but powerful design q A whole family of designs sharing similar design principles and a common instruction set

ARM powered products

Naming ARM q ARMxyz. TDMIEJFS – – – x: series y: MMU z: cache T: Thumb D: debugger M: Multiplier I: Embedded. ICE (built-in debugger hardware) E: Enhanced instruction J: Jazelle (JVM) F: Floating-point S: Synthesizible version (source code version for EDA tools)

ARM 7 applications

ARM 9 applications

ARM 11 applications

ARM Cortex. M applications • Dell E 4300 Latitude Laptop • instant boot-up for users and access to select applications, with multi-day battery lifetimes

ARM Cortex. A applications

ARM Cortex. R

Popular ARM architectures (selection) q ARM 7 TDMI – – 3 pipeline stages (fetch/decode/execute) High code density/low power consumption One of the most used ARM-version (for low-end systems) All ARM cores after ARM 7 TDMI include TDMI even if they do not include TDMI in their labels q ARM 9 TDMI – Compatible with ARM 7 – 5 stages (fetch/decode/execute/memory/write) – Separate instruction and data cache q ARM 11

ARM design philosophy q Small processor for lower power consumption (for embedded system) q High code density for limited memory and physical size restrictions q The ability to use slow and low-cost memory q Reduced die size for reducing manufacture cost and accommodating more peripherals

ARM architecture

ARM architecture q Load/store architecture q A large array of uniform registers q Fixed-length 32 -bit instructions q 3 -address instructions

RISC Architecture q Berkeley incorporated a Reduced Instruction Set Computer (RISC) architecture. q It has the following key features: – A fixed (32 -bit) instruction size with few formats; • CISC processors typically had variable length instruction sets with many formats. – A load–store architecture where instructions that process data operate only on registers and are separate from instructions that access memory; • CISC processors typically allowed values in memory to be used as operands in data processing instructions. – A large register bank of thirty-two 32 -bit registers, all of which could be used for any purpose, to allow the loadstore architecture to operate efficiently; • CISC register sets were getting larger, but none was this large and most had different registers for different purposes 22

RISC Organization q Hard-wired instruction decode logic – CISC processor used large microcode ROMs to decode their instructions q Pipelined execution – CISC processors allowed little, if any, overlap between consecutive instructions (though they do now) q Single-cycle execution – CISC processors typically took many clock cycles to completes a single instruction → Simple is beauty Compiler plays an important role 23

ARM Architecture vs. Berkeley RISC q Features used – Load/Store architecture – Fixed-length 32 -bit instructions – 3 -address instruction formats ADD d, S 1, S 2 ; d : = S 1 + S 2 q Features rejected – Register windows → costly • Use shadow (banked) registers in ARM – Delay branch • Badly with branch prediction – Single-cycle execution of all instructions • Most single cycle, many other take multiple clock cycles 24

ARM features q Different from pure RISC in several ways: – Variable cycle execution for certain instructions: multipleregister load/store (faster/higher code density) – Inline barrel shifter leading to more complex instructions: improves performance and code density – Thumb 16 -bit instruction set: 30% code density improvement – Conditional execution: improve performance and code density by reducing branch – Enhanced instructions: DSP instructions

Data Size and Instruction Set q ARM processor is a 32 -bit architecture q When used in relation to the ARM – Byte means 8 bits – Halfword means 16 bits (two bytes) – Word means 32 bits (four bytes) q Most ARM’s implement two instruction sets – 32 -bit ARM instruction set – 16 -bit Thumb instruction set 26

Data Types q ARM processor supports 6 data types – 8 -bits signed and unsigned bytes – 16 -bits signed and unsigned half-word, aligned on 2 -byte boundaries – 32 -bits signed and unsigned words, aligned on 4 -byte boundaries q ARM instructions are all 32 -bit words, word-aligned q Thumb instructions are half-words, aligned on 2 -byte boundaries 27

Processor Modes q The ARM has seven basic operating modes – User: unprivileged mode under which most tasks run – FIQ: entered when a high priority (fast) interrupts is raised – IRQ: entered when a low priority (normal) interrupts is raised – Supervisor: entered on reset and when a software interrupt instruction is executed – Abort: used to handle memory access violations – Undefined: used to handle undefined instructions – System: privileged mode using the same registers as user mode • Not in ARM architecture 1, 2, or 3 28

Processor Modes (cont. ) q Exception modes – FIQ, IRQ, Supervisor, Abort, and Undefined q Privileged modes – FIQ, IRQ, Supervisor, Abort, Undefined, and System 29

The Mode Bits q Mode changes by software control or external interrupts q Current program status register, CPSR 30

The Registers q ARM has 37 registers, all of which are 32 bits long – – 1 dedicated program counter 1 dedicated current program status register 5 dedicated saved program status registers 31 general purpose registers q The current processor mode governs which bank is accessible – Each mode can access • • A particular set of r 0 – r 12 registers A particular r 13 (stack pointer, SP) and r 14 (link register, LR) The program counter, r 15 (PC) The current program status register, CPSR – Privileged modes (except system) can access • A particular SPSR (Saved Program Status Register) 31

Register Banking r 0 r 1 usable in user mode r 2 r 3 exception modes only r 4 r 5 r 6 r 7 r 8_fiq r 8 r 9_fiq r 10 r 1 1 r 11_fiq r 12 CPSR system mode user mode r 13_svc r 14_svc r 13_fiq r 13 r 14 r 15 (PC) r 14_fiq SPSR_fiq mode r 13_abt SPSR_svc mode r 14_abt SPSR_abt abort mode r 13_irq r 13_und r 14_irq r 14_und SPSR_irq mode SPSR_und undefined mode 32

General Purpose Registers q The unbanked registers – r 0 – r 15 – user and system mode refer to the same physical registers q The banked registers – r 8_fiq – r 12_fiq, r 13_<mode>, and r 14_<mode> – The set of physical registers depend on the processor mode – r 13 is normally used as the stack pointer (SP) – r 14 is also known as the link register (LR), which is used to store the return address from a subroutine q Register 15, PC – r 15 is the program counter 33

Program Counter (r 15) q When the processor is executing in ARM state: – All instructions are 32 bits wide – All instructions must be word-aligned – Therefore the PC value is stored in bits [32: 2] with bits [1: 0] undefined (as instruction cannot be halfword) q When the processor is executing in Thumb state: – All instructions are 16 bits wide – All instructions must be halfword-aligned – Therefore the PC value is stored in bits [32: 1] with bits [0] undefined (as instruction cannot be byte-aligned) 34

Current Program Status Registers (CPSR) q Condition code flags – – N: Negative result form ALU Z: Zero result from ALU C: ALU Operation Carried out V: ALU operation o. Verflowed q Sticky overflow flag – Q flag – Architecture 5 TE only – Indicates if saturation has occurred during certain operations q Interrupt disable bits – I = 1, disable the IRQ – F = 1, disable the FIQ q T Bit – Architecture x. T only – T = 0, processor in ARM state – T = 1, processor in Thumb state q Mode bits – Specify the processor mode 35

Saved Program Status Register (SPSR) q Each privileged mode (except system mode) has associated with it a SPSR q This SPSR is used to save the state of CPSR when the privileged mode is entered in order that the user state can be fully restored when the user process is resumed q Often the SPSR may be untouched from the time the privileged mode is entered to the time it is used to restore the CPSR q If the privileged supervisor calls to itself the SPSR must be copied into a general register and saved 36

Exceptions q Exceptions are usually used to handle unexpected events which arise during the execution of a program, such as interrupts or memory faults, also cover software interrupts, undefined instruction traps, and the system reset q Three groups: – Exceptions generated as the direct effect of executing an instruction • Software interrupts, undefined instructions, and prefetch abort – Exceptions generated as a side effect of an instruction • Data aborts – Exceptions generated externally • Reset, IRQ and FIQ 37

Exception Entry (1/2) q When an exception arises – ARM completes the current instruction as best it can (except that reset exception) – handle the exception which starts from a specific location (exception vector). q Processor performs the following sequence: – Change to the operating mode corresponding to the particular exception – Stores the return address in LR_<mode> – Copy old CPSR into SPSR_<mode> – Set appropriate CPSR bits • If core currently in Thumb state then ARM state is entered. • Disable IRQs by setting bit 7 • If the exception is a fast interrupt, disable further faster interrupt by setting bit 6 of the CPSR 38

Exception Entry (2/2) – Force PC to relevant vector address Priority Exception Mode vector address 1 Reset SVC 0 x 0000 2 Data abort (data access memory fault) Abort 0 x 00000010 3 FIQ (fast interrupt ) FIQ 0 x 0000001 C 4 IRQ (normal interrupt) IRQ 0 x 00000018 5 Prefetch abort (instruction fetch memory fault) Abort 0 c 0000000 C 6 Undefined instruction UND 0 x 00000004 Software interrupt (SWI) SVC 0 x 00000008 q Normally the vector address contains a branch to the relevant routine q Exception handler use r 13_<mode> and r 14_<mode> to hold the stack point and return address 39

Exception Return q Once the exception has been handled, the user task is normally resumed q The sequence is – Any modified user registers must be restored from the handler’s stack – CPSR must be restored from the appropriate SPSR – PC must be changed back to the relevant instruction address q The last two steps happen atomically as part of a single instruction 40

Memory Organization q Word, half-word alignment (xxxx 00 or xxxxx 0) q ARM can be set up to access data in either littleendian or big-endian format, through they default to little-endian. 41

Features of the ARM Instruction Set q Load-store architecture – Process values which are in registers – Load, store instructions for memory data accesses q 3 -address data processing instructions q Conditional execution of every instruction q Load and store multiple registers q Shift, ALU operation in a single instruction q Open instruction set extension through the coprocessor instruction q Very dense 16 -bit compressed instruction set (Thumb) 42

Coprocessors – Up to 16 coprocessors can be defined – Expands the ARM instruction set – Each coprocessor can have up to 16 private registers of any reasonable size – Load-store architecture 43

Thumb q Thumb is a 16 -bit instruction set – Optimized for code density from C code – Improved performance form narrow memory – Subset of the functionality of the ARM instruction set q Core has two execution states – ARM and Thumb – Switch between them using BX instruction q Thumb has characteristic features: – Most Thumb instructions are executed unconditionally – Many Thumb data process instruction use a 2 -address format – Thumb instruction formats are less regular than ARM instruction formats, as a result of the dense encoding. 44

I/O System q ARM handles input/output peripherals as memorymapped with interrupt support q Internal registers in I/O devices as addressable locations with ARM’s memory map read and written using load-store instructions q Interrupt by normal interrupt (IRQ) or fast interrupt (FIQ) q Interrupt input signals are level-sensitive and maskable q May include Direct Memory Access (DMA) hardware 45

ARM instruction set 46

q ARM assembly language program – ARM development board or ARM emulator q ARM instruction set – Standard ARM instruction set – A compressed form of the instruction set, a subset of the full ARM instruction set is encoded into 16 -bit instructions – Thumb instruction – Some ARM cores support instruction set extensions to enhance signal processing capabilities 47

Instructions q Data processing instructions q Data transfer instructions q Control flow instructions 48

Conditional Execution q Most instruction sets only allow branches to be executed conditionally. q However by reusing the condition evaluation hardware, ARM effectively increase number of instruction – All instructions contain a condition field which determines whether the CPU will execute them – Non-executed instruction still take up 1 cycle • To allow other stages in the pipeline to complete q This reduces the number of branches which would stall the pipeline – Allows very dense in-line code – The time penalty of not executing several conditional instructions is frequently less than overhead of the branch or instruction call that would otherwise be needed 49

Condition code 31 28 27 0 cond Opcode [31: 28] Mnemonic extension Interpretation Status flag state for execution 0000 EQ Equal / equals zero Z set 0001 NE Not equal Z clear 0010 CS/HS Carry set / unsigned higher or some C set 0011 CC/LO Carry clear / unsigned lower C clear 0100 MI Minus / negative N set 0101 PL Plus / positive or zero N clear 0110 VS Overflow V set 0111 VC No overflow V clear 1000 HI Unsigned higher C set and Z clear 1001 LS Unsigned lower or same C clear or Z set 1010 GE Signed greater than or equal N equals V 1011 LT Signed less than N is not equal to V 1100 GT Signed greater than Z clear and N equals V 1101 LE Signed less than or equal Z sets or N is not equal to V 1110 AL Always any 1111 NV Never (do not use!) none 50

Example of Conditional Execution q An unusual feature of the ARM instruction set is that conditional execution applies not only to branches but to all ARM instructions CMP r 0, #5 BEQ Bypass CMP r 0, #5 ; if (r 0!=5) ADDNE r 1, r 0 ADD r 1, r 0 ; {r 1=r 1+r 0} SUBNE r 1, r 2 SUB r 1, r 2 Bypass … q Whenever the conditional sequence is 3 instructions or fewer it is better (smaller and faster) to exploit conditional execution than to use a branch CMP r 0, r 1 if((a==b)&&(c==d)) e++; CMPEQ r 2, r 3 ADDEQ r 4, #1 51

Using and Updating the condition Field q To execute an instruction conditionally, simply postfix it with the appropriate condition: – For example an add instruction takes the form • ADD r 0, r 1, r 2 ; r 0 = r 1 + r 2 (ADDAL) – To execute this only if the zero flag is set • ADDEQ r 0, r 1, r 2 ; r 0 = r 1 + r 2 iff zero flag set q By default, data processing operations do not affect the condition flags – With comparison instructions this is the only effect q To cause the condition flags to be updated, the S bit of the instruction needs to be set by postfixing the instruction (and any condition codes) with an “S”. – For example to add two numbers and set the condition flags: • ADDS r 0, r 1, r 2 ; r 0 = r 1 + r 2 and set flags 52

Data Processing Instruction (1/3) q Consist of – – Arithmetic (ADD, SUB, RSB) Logical (BIC, AND) Compare (CMP, TST) Register movement (MOV, MVN) q All operands are 32 -bit wide; come from registers or specified as literal in the instruction itself q Second operand sent to ALU via barrel shifter q 32 -bit result placed in register; long multiply instruction produces 64 -bit result q 3 -address instruction format – 2 source operands and 1 destination register – One source is always a register, the second may be a register, a shifted register or an immediate value 53

Data Processing Instruction (2/3) q Allows direct control of whether or not the condition codes are affected by S bit (condition code unchanged when S = 0) – N = 1 if the result is negative; 0 otherwise (i. e. N = bit 31 of the result) – Z = 1 if the result is zero; 0 otherwise – C = 1 carry out from the ALU when ADD, ADC, SUB, SBC, RSB, RSC, CMP, or CMN; carry out from the shifter – V = 1 if overflow from bit 30 to bit 31; 0 if no overflow (V is preserved in non-arithmetic operations) q PC may be used as a source operand (address of the instruction plus 8) except when a register-specified shift amount is used q PC may be specified as the destination register, the instruction is a form of branch (return from a subroutine) 54

Data Processing Instruction (3/3) 31 28 27 26 25 24 cond 00 # 21 20 19 opcode S 16 15 Rn 12 11 0 operand 2 Rd destination register first operand register set condition codes arithmetic/logic function 25 11 8 7 #rot 1 0 8 -bit immediate alignment 11 7 #shift 25 0 6 5 4 Sh 3 0 Rm 0 immediate shift length shift type second operand register 11 8 7 Rs 0 6 5 4 Sh 1 3 0 Rm register shift length 55

Simple Register Operands (1/2) q Arithmetic Operations ADD ADC SUB SBC RSB RSC r 0, r 1, r 2 r 0, r 1, r 2 ; r 0: =r 1+r 2+C ; r 0: =r 1–r 2+C– 1 ; r 0: =r 2–r 1, reverse subtraction ; r 0: =r 2–r 1+C– 1 – By default data processing operations do no affect the condition flags q Bit-wise Logical Operations AND ORR EOR BIC r 0, r 1, r 2 ; r 0: =r 1 ANDr 2 ; r 0: =r 1 ORr 2 ; r 0: =r 1 XORr 2 ; r 0: =r 1 AND(NOT r 2), bit clear 56

Simple Register Operands (2/2) q Register Movement Operations – Omit 1 st source operand from the format MOV r 0, r 2 MVN r 0, r 2 ; r 0: =NOT r 2, move 1’s complement q Comparison Operations – Not produce result; omit the destination from the format – Just set the condition code bits (N, Z, C and V) in CPSR CMP CMN TST TEQ r 1, r 2 ; set cc cc on on r 1 r 1 - r 2, compare + r 2, compare negated AND r 2, bit test XOR r 2, test equal 57

Immediate Operands q Replace the second source operand with an immediate operand, which is a literal constant, preceded by “#” ADD r 3, #1 AND r 8, r 7, #&FF ; r 3: =r 3+1 ; r 8: =r 7[7: 0], &: hexadecimal q Since the immediate value is coded within the 32 bits of the instruction, it is not possible to enter every possible 32 -bit value as an immediate. Immediate = (0 → 255) × 22 n where 58

Shift Register Operands – ADD r 3, r 2, r 1, LSL#3 : = r 2 + 8 * r 1 ; r 3 • A single instruction executed in a single cycle q LSL: Logical Shift Left by 0 to 31 places, 0 filled at the lsb end q LSR, ASL (Arithmetic Shift Left), ASR, ROR (Rotate Right), RRX (Rotate Right e. Xtended by 1 place) – ADD r 5, r 3, LSL r 2 ; r 5: =r 5+r 3*2 r 2 – MOV r 12, r 4, ROR r 3 ; r 12: =r 4 rotated right by value of r 3 59

Multiply Instructions (1/2) q 32 -bit product (Least Significant) – MUL{<cond>}{S} Rd, Rm, Rs – MLA{<cond>}{S} Rd, Rm, Rs, Rn MUL r 4, r 3, r 2; r 4: =(r 3*r 2)[31: 0] MLA r 4, r 3, r 2, r 1; r 4: =(r 3*r 2+r 1)[31: 0] q 64 -bit Product – <mul>{<cond>}{S} Rd. Hi, Rd. Lo, Rm, Rs – <mul> is UMULL, UMLAL, SMULL, SMLAL 60

Multiply Instructions (2/2) q Booth’s algorithm is used to perform integer multiplication – Instructions will early terminate wherever possible – On ARM 7 TDMI Mul will execute in minimum of 2 clock cycles and maximum of 5 clock cycles q Restrictions on use: – Rd and Rm cannot be the same register (can be avoided by swapping over Rm and Rs – multiplication is commutative) 61

Multiplication by a Constant q Multiplication by a constant equals to a ((power of 2) +/- 1) can be done in a single cycle – Using MOV, ADD or RSB with an inline shift q Example: r 0 = r 1 * 5 q Example: r 0 = r 1 + (r 1 * 4) – ADD r 0, r 1, LSL #2 ; r 0: =r 1+r 1*4 q Can combine several instruction to carry out other multiplies q Example: r 2 = r 3 * 119 q Example: r 2 = r 3 * 17 * 7 q Example: r 2 = r 3 * (16 + 1) * (8 - 1) – ADD r 2, r 3, LSL #4 – RSB r 2, LSL #3 ; r 2: =r 3*17 ; r 2: =r 2*7 62

Loading Constants (1/2) q No single ARM instruction can load a 32 -bit immediate constant directly into a register – All ARM instructions are 32 -bit long – ARM instructions do not use the instruction stream as data q The data processing instruction format has 12 bits available for operand 2 (refer to P. 44) – If used directly, this would only give a range of 4096 q Instead it is used to store 8 -bit constants, give a range of 0255 q These 8 bits can then be rotated right through an even number of positions q This gives a much larger range of constants that can be directly loaded, through some constants will still need to be loaded from memory 63

Loading Constant (2/2) q To load a constant, simply move the required value into a register – the assembler will convert to the rotate form for us – MOV r 0, #4096 ; MOV r 0, #&1000 (0 x 40 ror 26) q The bitwise complements can also be formed using MVN: – MOV r 0, #&FFFF ; MVN r 0, #0 q Value that cannot be generated in this way will cause an error 64

Loading 32 -bit Constants q To allow larger constants to be loaded, the assembler offers a pseudo-instruction: – LDR Rd, =const q This will either: – Produce a MOV or MVN instruction to generate the value (if possible) or – Generate a LDR instruction with a PC-relative address to read the constant from a literal pool (constant data area embedded in the code) q For example – MOV r 0, =&FF – LDR r 0, =&5555 ; MOV r 0, #0 x. FF ; LDR r 0, [PC, #Imm 10] q As this mechanism will always generate the best instruction for a given case, it is the recommended way of loading constant 65

Data Transfer Instructions q Three basic forms to move data between ARM registers and memory – Single register load and store instruction • A byte, a 16 -bit half word, a 32 -bit word – Multiple register load and store instruction • To save or restore workspace registers for procedure entry and exit • To copy blocks of data – Single register swap instruction • A value in a register to be exchanged with a value in memory • To implement semaphores to ensure mutual exclusion on accesses 66

Single Register Data Transfer q Word transfer – LDR / STR q Byte transfer – LDRB / STRB q Halfword transfer – LDRH / STRH q Load single byte or halfword-load value and sign extended to 32 bits – LDRSB / LDRSH q All of these can be conditionally executed by inserting the appropriate condition code after STR/LDR – LDREQB 67

Addressing mode q Register-indirect addressing q Base-plus-offset addressing – Base register • r 0 – r 15 – Offset, and or subtract an unsigned number • Immediate • Register (not PC) • Scaled register (only available for word and unsigned byte instructions) q Stack addressing q Block-copy addressing 68

Register-Indirect Addressing q Use a value in one register (base register) as a memory address LDR r 0, [r 1] STR r 0, [r 1] ; r 0: =mem 32[r 1] ; mem 32[r 1]: =r 0 q Other forms – Adding immediate or register offsets to the base address 69

Initializing an Address Pointer q A small offset to the program counter, r 15 – ARM assembler has a “pseudo” instruction, ADR q As an example, a program which must copy data from TABLE 1 to TABLE 2, both of which are near to the code Copy ADR r 1, TABLE 1 ; r 1 points to TABLE 1 ADR r 2, TABLE 2 ; r 2 points to TABLE 2 … TABLE 1 … ; <source> … ; <destination> TABLE 2 70

Base-plus-offset Addressing (1/2) q Pre-indexing LDR r 0, [r 1, #4] ; r 0: =mem 32[r 1+4] – Offset up to 4 K, added or subtracted, (# -4) q Post-indexing LDR r 0, [r 1], #4 ; r 0: =mem 32[r 1], r 1: =r 1+4 – Equivalent to a simple register-indirect load, but faster, less code space q Auto-indexing LDR r 0, [r 1, #4]! ; r 0: =mem 32[r 1+4], r 1: =r 1+4 – No extra time, auto-indexing performed while the data is being fetched from memory 71

Base-plus-offset Addressing (2/2) 72

Multiple Register Data Transfer (1/2) q The load and store multiple instructions (LDM/STM) allow between 1 and 16 registers to be transferred to or from memory – Order of register transfer cannot be specified, order in the list is insignificant – Lowest register number is always transferred to/from lowest memory location accessed q The transferred registers can be either – Any subset of the current bank of registers (default) – Any subset of the user mode bank of registers when in a privileged mode (postfix instruction with a “^”) q Base register used to determine where memory access should occur – 4 different addressing modes – Base register can be optionally updated following the transfer (using “!”) 73

Multiple Register Data Transfer (2/2) q These instruction are very efficient for – Moving block of data around memory – Saving and restoring context – stack q The direction that the base pointer moves through memory is given by the postfix to the STM/LDM instruction – – STMIA/LDMIA: Increment After STMIB/LDMIB: Increment Before STMDA/LDMDA: Decrement After STMDB/LDMDB: Decrement Before q Allow any subset (or all, r 0 to r 15) of the 16 registers to be transferred with a single instruction LDMIA r 1, {r 0, r 2, r 5} ; r 0: =mem 32[r 1] ; r 2: =mem 32[r 1+4] ; r 5: =mem 32[r 1+8] 74

Stack Processing q The stack type to be used is given by the postfix to the instruction: – – STMFD/LDMFD: Full Descending stack STMFA/LDMFA: Full Ascending stack STMED/LDMED: Empty Descending stack STMEA/LDMEA: Empty Ascending stack q Note: ARM Compilers will always use a Full descending stack 75

Swap Memory and Register Instructions q Syntax – SWP{<cond>}{B} Rd, Rm, [Rn] – Rd <- [Rn], [Rn] <- Rm q Combine a load and a store of a word or an unsigned byte in a single instruction q Example ADR r 0, SEMAPHORE SWPB r 1, [r 0] ; exchange byte 76

Status Register to General Register Transfer instructions q Syntax – MRS{<cond>} Rd, CPSR|SPSR q The CPSR or the current mode SPSR is copied into the destination register. All 32 bits are copied. q Example MRS r 0, CPSR MRS r 3, SPSR 77

General Register to Status Register Transfer instructions q Syntax – MSR{<cond>} CPSR_<field>|SPSR_<field>, #<32 bit immediate> – MSR{<cond>} CPSR_<field>|SPSR_<field>, Rm – <field> is one of • • c – the control field PSR[7: 0] x – the extension field PSR[15: 8] s – the status field PSR[23: 16] f – the flag field PSR[31: 24] q Example – Set N, X, C, V flags • MSR CPSR_f, #&f 0000000 78

Branch Instructions q Syntax – Branch: – Branch with Link: B{<cond>} Label BL{<cond>} subroutine_label Link bit 0 = Branch 1 = Branch with Link Condition field q The PC-relative offset for branch instructions is calculated by: – Taking the difference between the branch instruction and the target address minus 8 (to allow for the pipeline) – This gives a 26 bit offset which is right shifted 2 bits (as the bottom two bits are always zero as instruction are word-aligned) and stored into the instruction encoding – This gives a range of +/- 32 Mbytes. 79

Conditional Branch (1/2) q The branch has a condition associated with it and it is only executed if the condition codes have the correct value – taken or not taken Loop MOV … ADD CMP BNE r 0, #0 ; initialize counter r 0, #1 ; increment loop counter r 0, #10 ; compare with limit Loop ; repeat if not equal ; else fail through 80

Conditional Branch (2/2) 81

Examples q Unconditional jump LABEL B … … LABEL q Loop ten times Loop MOV r 0, #10 … SUBS r 0, #1 BNE Loop … q Conditional subroutine call CMP r 0, #5 BLLT SUB 1 ; if r 0<5, ; call sub 1 BLGE SUB 2 ; else call ; SUB 2 q Call a subroutine SUB BL SUB … … MOV PC, r 14 82

Branch, Branch with Link and e. Xchange q B{L}X{<cond>} Rm – The branch target is specified in a register, Rm – Bit[0] of Rm is copied into the T bit in CPSR; bit[31: 1] is moved into PC – If Rm[0] is 1, the processor switches to execute Thumb instructions and begins executing at the address in Rm aligned to a half-word boundary by clearing the bottom bit – If Rm[0] is 0, the processor continues executing ARM instructions and begins executing at the address in Rm aligned to a word boundary by clearing Rm[1] q BLX <target address> – Call Thumb subroutine from ARM – The H bit (bit 24) is also added into bit 1 of the resulting addressing, allowing an odd half-word address to be selected for the target instruction which will always be a Thumb instruction 83

Software Interrupt (SWI) q SWI{<cond>}<24 -bit immediate> – Used for calls to the operating system and is often called a “supervisor call” – It puts the processor into supervisor mode and begins executing instruction from address 0 x 08 (refer to P. 21) • Save the address of the instruction after SWI in r 14_svc • Save the CPSR in SPSR_svc • Enter supervisor mode and disable IRQs by setting CPSR[4: 0] to 100112 and CPSR[7] to 1 • Set PC to 0816 and begin executing the instruction there – The 24 -bit immediate does not influence the operation of the instruction but may be interpreted by the system code 84

Supervisor Calls q The supervisor is a program which operates at a privileged level, which means that it can do things that a use-level program cannot do directly (e. g. input or output) q SWI instruction – Software interrupt or supervisor call SWI_Write. C SWI_Exit ; output r 0[7: 0] ; return to monitor program 85

Coprocessor Instructions q The ARM architecture supports 16 coprocessors q The instructions for each coprocessor occupy a fixed part of the ARM instruction set – If the appropriate coprocessor is not present in the system, an undefined instruction exception occurs. q There are three types of coprocessor instruction – Coprocessor data processing • CDP: Initiate a coprocessor data processing operation – Coprocessor register transfers • MRC: Move to ARM register from coprocessor register • MCR: Move to Coprocessor register from ARM register – Coprocessor memory transfers • LDC: Load coprocessor register from memory • STC: Store from coprocessor register to memory 86

ARM Instruction Set Summary (1/4) 87

ARM Instruction Set Summary (2/4) 88

ARM Instruction Set Summary (3/4) 89

ARM Instruction Set Summary (4/4) 90

ARM Instruction Set Format 91

Summary q ARM architecture – Load/Store architecture – Fixed-length 32 -bit architecture – 3 -address instruction formats – 37 registers – Little endian/big endian – Memory maped IO – Coprocessors q Instruction set – Conditional execution – 32 -bit ARM instruction • Data processing instructions – Arithmetic/Logical/Compare /Multiply • Data transfer instructions – Load/Store/Swap • Control flow instructions – Branch/SWI – 16 -bit Thumb instruction (next class) 92

Content q. The ARM processor q. ARM instruction set q. Summary

Homework q ARM architecture – Which are the characteristics of ARM architecture? What advantages do they bring? 94