Microprocessor History Early microprocessors PMOS technology slow and

Microprocessor History

Early microprocessors • PMOS technology – slow and awkward to interface with TTL family • 4 bit processor • Instructions were executed in about 20 µs. • Intel 4004 the first MP. 4 K nibbles address space. • Intel 8008 - can manipulate a whole byte. • 16 Kbytes address space • 50, 000 operations/second.

N-channel MOSFET • 1970. • Faster than P-MOS. • Work with +ve supply; easy to interface with TTL. • 1973 Intel 8080 MP. • 500, 000 operations/second. • 64 K bytes memory. • Upward software compatible with 8008. • Other brands are MC 6800, Fairchild’s F-8

Basic types of MP • Two types – Single component microprocessors – Bit sliced microprocessors • Can be cascaded to allow functioning systems with word size from 4 bits to 200 bits.

Single component M Computer • Composed of – A processor – read only memory (for program storage) – Read/Write memory (for data storage) – Input/output connections for interfacing – Timer as event counter • Intel 8048, Motorola 6805 R 2. – Oven, washing machine, dish washer etc.

Modern MP • 8, 16, 32, 64 bits are available. • Intel 8085, Motorola 6800 – 8 bit word 16 bit address. • Intel 8088, 8086, Motorola 68000 – 16 bits word, 20 bits address. • 80186 – never used. • 286 – real mode and protected mode; 16 MB memory • 386 – paging, 4 GB memory, 32 bits word • 486 – math coprocessor, L 1 cache

Modern MP • Pentium – 64 bits i/o off the chip but process 32 bits word, exception floating point processed 64 bits, cache doubled, instruction pipelining. • Pentium Pro – L 2 cache, Improved pipelining • Pentium MMX – Multi-Media extensions, 57 new inter instruc mostly used for multimedia programming • Pentium II, IV – Pentium pro with MMX tech, increased L 2 cache, full 64 bit operation • RISC – Reduced instruction set processor, uniform length instruc, faster in operation, cannot perform may different thing as CISC.

MP based system MP memory IO device

Basic MP architecture – 0000 H for 8085 – FFFF 0 H for 8086, 8088 Data Bus Instruction Register Control Bus ALU • Fetch, decode, execute. • PC increment. • First instruction is a fetch control Address Bus AF, Register Array BC, DE, HL, SP, PC many more

Memory Interfacing and IO decoding

• Interfacing needs bus • Isolation and separation of signals from different devices connected to MP. – Unidirectional – Bidirectional • LS 373, 244

Memory map • Pictorial representation of the whole range of memory address space. – Defines which memory system is where, their sizes etc. • Address space or range. – 8086 has 1 M address space in minimum mode. – 8085 has 64 K address sspace.

Address Decoding • Address decoder is a digital ckt that indicates that a particular area of memory is being addressed, or pointed to, by the MP. • Absolute address decoding – Decode an address to one single output – Decode 10110 so that u can get a signal from the decoder when it receives exactly that bit pattern. • Partial address decoding – Some bits are used as don’t care so that decoder gives a signal for a range of consecutive bit patterns.

Absolute decoding 1 0 1 1 0 a b c d e Active low o/p signal Can use decoder IC with gates to achieve exact decoded o/p 1 0 1 3 to 8 line dcd 0 o/p 7 Logic 1 8 input NAND gate implementation

Partial decoding • When a range of addresses are deconded then it is called partial decoding. For example, if we need to generate a control signal for an address generated by the MP within the range FFF 0 – FFFF, then it is called partial decoding. 1 1 1 x x A 15 A 14 A 4 • Decoder, multiplexer can be used for address decoding

Bus control signals IO/M RD 8085 MEMR IOWR MEMWR WR IOWR

Interfacing A Memory Chip • 2 K Byte memory • Memory address space of the chip: 8800 H to 8 FFFH IO/M A 13 A 12 A 11 A 15 A 14 A 13 A 12 A 11 A 10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 1 0 0 0 1 X X X X X 8 8 - F 0 - F A 14 A 15 E 1 E 2 E 3 3 to 8 decoder Q 1 A 10 A 9 A 0 RD WR MEMSEL CE Memory Chip D 7 D 6 D 0

Reading a byte from memory • Reading an Opcode 4 Fh in memory location 2005 H. – PC places the 16 bit address 2005 H of the memory location on the address bus. – Control unit sends the memory read signal (MEMR) to enable O/P buffer of the memory chip. – The value 4 Fh stored in location 2005 H is placed on the data bus and transferred to instruction decoder of the MP.

8085 functional block diagram Serial I/O control Interrupt control Accumu External Add/data bus(8) MUX Temp Reg Instru Register (8) Instru Decoder Reg Select Flags W Z Temp Reg (8) B C (8) D E (8) H L (8) Stack pointer (16) Program counter (16) Incrementer/decrementer Latch (16) Address buffer (8) Timing & control External Address bus(8) Data/Add buffer (8)

MP operations 1. MP initiated Operations • Memory/IO read/write 2. Internal operations • • • Store 8 -bit data Arithmetic and logical operations Test for conditions Sequence the execution of Instruction Stack operation 3. Peripheral operations • Reset, Interrupt, ready and hold

Flag register S Z AC P CY 1. S : after the execution of an arithmetic operation, if bit 7 of the result is 1, then sign flag is set. 2. Z : bit is set if ALU operation results a zero in the Acc or registers. 3. AC: bit is set, when a carry is generated by bit 3 and passed on bit 4. 4. P: parity bit is set when the result has even number of 1 s. 5. CY = carry is set when result generates a carry. Also a borrow flag.

Accumulator • Hold data for manipulation (arithmetic, logical). • Whenever the operation combines two words, either arithmetically or logically, the accumulator contains one word (say A) and the other word (say B) may be contained in a register or in memory location. After the operation the result is placed in the Acc replacing the word A. • Major working register. MP can directly work on Acc. • Programmed data transfer.

General purpose registers • Six registers. • B, C, D, E, H and L can store 8 bit data. • They can be combined to perform some 16 bit operation.

ALU • Arithmetic logic unit. • Two input ports, one output port. • Perform AND, OR, Ex. OR, Add, subtract, complement, Increment, Decrement, shift left, shift right. • ALUs one temporary registers are connected to MPs internal bus from which it can take data from any registers. It can place data directly to data bus through its single output port.

Program counter • Its job is to keep track of what instruction is being used and what the next instruction will be. • For 8085 it is 16 bit long. • Can get data from internal bus as well as memory location. • PC automatically increments to point to the next memory during the execution of the present instruction. • PC value can be changed by some instructions.

Stack pointer • 16 bit register acts as memory pointer. • Can save the value of the program counter for later use. • points to a region of memory which is called stack. follows LIFO algorithm. • After every stack operation SP points to next available location of the stack. Usually decrements.

Memory address register • PC sends address to MAR points to the location of the memory where the content is to be fetched from. • PC increments but MAR does not. • If the content is an instruction, IR decodes it. During execution if it is required to fetch another word from memory, PC is loaded with the value • PC again sends it to the MAR and fetch operation starts.

Instruction register • Holds instruction the microprocessor is currently being executed. • 8 bit long.

others • Instruction decoder. • Control logic. • Internal data bus.

Machine cycle and Timing dia • MP works in steps of clock. Each clock cycle is called T-state. • A machine cycle is composed a few T-states and performs either read or write operations. • All MP instructions are divided into few machine cycles. – – – Opcode fetch Memory read Memory write IO read IO write

Timing diaga. of Memory cycle T 1 T 2 T 3 CLK A 15 -A 8 A 7 -A 0 Data from memory AD 7 -AD 0 A 7 -A 0 Data from MPU ALE IO/M RD MEMRD READ Cycle WR MEMWR WRITE Cycle

MVI A, 32 H Instruction 2000 H 2001 H 3 EH ; MVI A, 32 H M 1 (Opcode-fetch) T 1 A 15 -A 8 AD 7 -AD 0 T 2 T 3 20 H; high-order address 00 H; loworder Add M 2 (Memory Read) T 4 Unspecified 3 E; opcode T 1 T 3 T 2 20 H; High-order address 01 H; loworder Add 32 H; Data ALE Status IO/M=0, S 1=1, S 0=1; opcode fetch RD Status IO/M=0, S 1=1, S 0=0; data read

Execution time • • • Clock frequency f = 2 MHz T-state = (1/f) = 0. 5 µs Exec time for opcode fetch= (4 Tx 0. 5)=2 µs. Exec time for memory read = 3 Tx 0. 5=1. 5 µs. Exec time for instruction = 7 Tx 0. 5 = 3. 5 µs.

8085 5 V GND 40 20 • 40 pin DIP. • +5 V • 3 - 5 MHz – – ADD BUS DATA BUS CONTROL STATUS POWER SUPPLY AND FREQ – EXTERNALLY INITIATED SIGNALS – SERIAL I/O PORTS SID 5 SOD 4 X 1 X 2 21 – 28 HIGH ORDER ADD BUS TRAP 6 RST 7. 5 7 RST 6. 5 8 RST 5. 5 9 INTR 10 12 – 19 MUX ADD/ DATA BUS READY 35 HOLD 39 29 S 0 30 ALE 33 S 1 RESET IN 36 34 IO/M’ 32 RD’ INTA 11 HLDA 38 3 37 RESET OUT 31 WR’ CLK OUT

• 8085 has the clock generation circuit on the chip. 8085 can operate maximum 3. 03 MHz and 8085 A-2 can operate maximum 5 MHz clock. • crystal, LC tuned, external clock ckt. • the frequency at x 1 x 2 is divided by 2 internally. This means that in order to obtain 3. 03 MHz, a clock source of 6. 06 MHz must be connected to X 1 X 2. • for crystals with less than 4 MHz, a capacitor of 20 p. F should be connected X 2 and ground. X 1 X 2 GND X 1 X 2

ADD/DATA bus • Address bus 16 bits A 15 – A 8 to A 15 unidirectional. Higher 8 bit Address bus. higher 8 bit – AD 0 to AD 7 multiplexed with data. This pins A are bidirectional when used as data bus. 8 • Data bus 8 bit long: AD 0 to AD 7 ALE AD 7 AD 6 AD 5 AD 0 G D Q’ Address bus. Lower 8 bit OC GND Data bus

Control signals IO/M’ • ALE – active high output Machine cycle used to latch the lower 8 Opcode fetch 0 address bits. Memory read 0 • RD, WR - active low output signals. Memory write 0 • IO/M – output signal to I/O read 1 differentiate memory and I/O write 1 Interrupt Ackn 1 IO operation. Z • S 1 and S 0 – status output Halt Z signal. Identify various Hold Reset Z operations. S 1 S 0 Control signals 1 1 RD=0 1 0 RD=0 0 1 WR=0 1 1 INTA=0 0 0 X X RD, WR =Z and INT

External control signals • INTR – interrupt request. Input signal • INTA – interrupt acknowledge. o/p signal. • RST 7. 5, RST 6. 5, RST 5. 5 – restart interrupts. Vectored interrupts. Higher priority. • TRAP - Nonmaskable interrupt. Highest priority. • Hold – request for the control of buses. I/P signal • HLDA – Hold Acknowledge. O/P signal • READY – I/P signal. When low, Mp waits for integral number of clock cycles until it goes high.

Interfacing I/O devices • Port address • Two ways to interface – IO mapped I/O – Memory mapped IO • 8085 – IO address space 256 (i. e 28) – Memory address space 64 K (i. e 216)

Interfacing approach • Port address – An address where a buffer or latch is connected through which actual data transfer takes place between MP and IO device. – Input port or output port. • IO mapped IO – The port address of the IO devices is mapped into the IO address space – Port address is an eight binary number. IN/OUT instructions are used data transfer. • Memory Mapped IO – The port address of the IO device is mapped into the memory address space. – Port address is a 16 bit binary number. LDA, STA etc memory related instructions are used for data transfer.

Logic devices for interfacing • Tri-state buffer – At input port – 74 LS 244: unidirectional octal buffer – 74 LS 245: bidirectional octal buffer • Latches – At output port – 74 LS 373: Octal D type latch • Decoder – For address decoding, port selection, but control signal – 74 LS 138: 3 -to-8 decoder most commonly used. • Encoder – For interfacing keyboard – 74 LS 148: 8 to 3 priority encoder

Peripheral I/O instructions • port address: 50 H 2050 D 3 OUT 50 H sends acc content to I/O address 50 H 2051 50 • Let input port address is 30 H 2150 DB IN 30 H reads content from I/O address 30 H and 2151 30 stores the value in accum

Device selection & Data Transfer IOR or IOW Address lines Decoder NOR Latch Or Tri-state Buffer To Peripherals Enable Data bus • Decode the IO address. • Combine it with control the signal to generate a unique IO select pulse that is generated only when both signals are asserted. • Use it to activate the IO port • Address decoding can be absolute or partial

IN 30 H instruction M 1 T 2 M 2 T 3 T 4 T 1 T 2 M 3 T 1 T 2 T 3 CLK A 15 -A 8 AD 7 -AD 0 ALE IO/M RD MEMRD IORD unspec ified 21 H 50 H DB from memory 21 H 51 H Port add 30 H Port addre 30 H Port add 30 H Data from Accumula

OUT 50 H instruction M 1 T 2 M 2 T 3 T 4 T 1 T 2 M 3 T 1 T 2 T 3 CLK A 15 -A 8 AD 7 -AD 0 ALE IO/M RD MEMRD WR IOWR unspec ified 20 H 50 H Opcode D 3 20 H 51 H Port add, 50 H Port addre 50 H Port add 50 H Data from Accumula

Interfacing LED for display • Given port add: FFH • Use octal latch as o/p port. • Steps for IO select pulse: – Decode FF – Use IO/M to make the port I/O mapped only – Use WR signal to write data to the port

MVI A, data OUT FFH HLT IOADR WR IOSEL IO/M G D 7 D 6 D 0 D FF Octal D- latch * To interface a 7 -segment display you need to decide about the type of 7 -segment: common anode or common cathode * Power supply connection to the LED segments will be opposite. * For common cathode a 0 is sent to the respective pin to lit it up. A 7 A 1 A 0 OE +5 V

Interfacing DIP switches • Let port address: 07 H – 00 H A • Partial decoding A A • Must use pull-up resistors. IN 07 H instruction reads a byte into accumulator from port 07 H A 4 7 6 5 A 3 IO/M E 1 E 2 E 3 3 to 8 decoder Q 0 RD IOSEL OE D 7 D 1 D 0 +5 V

Interfacing 7 segment LED o/p address F 9 h A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 1 1 1 1 0 1 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 IO/M E 1 E 2 E 3 3 to 8 decoder WR Q 5 IOSEL OE +5 V D 7 D 6 74 LS 377 D 0 D FF 7 -Segment

8085 Interrupts • 5 interrupt pins • Maskable – INTR – RST 5. 5, RST 6. 5, RST 7. 5 • Non-Maskable – TRAP: cannot be disabled by instruction. • TRAP has highest priority • Once a interrupt is serviced all interrupts except TRAP is disabled

TRAP • cannot be disabled by instruction • Requires a High level with a leading eadge at the pin. • braches to location 0024 H. • disabled at the falling edge of the signal at the pin.

RST 7. 5, 6. 5, 5. 5 • can be enabled or disabled by SIM (Set Interrupt Mask). • 7. 5 – Leading edge. branches to 003 CH. • 6. 5, 5. 5 – High level. – 6. 5: branches to 0034 H – 5. 5: branches to 0020 H

INTR Interrupt process • enable by writing EI. • mp checks INTR line at each instruction. • if INTR is high, mp completes the current instr, disables Interrupt Flip-flop, sends INTA signal. • An RST instru is inserted by INTA through external hardware. • Mp saves the memory address of the next instru into stack. Program control is transferred to CALL location. The service routine starts at CALL location. • At the end of the subroutine Int Flag is enabled again by EI instru. • The last instr of the subroutine is RET to trasfer back the prog control to its orginal address.

RST instructions • 8 RST instructions +5 v 1 1 Enable EF to data bus 1 1 0 1 Binary code Mnemo nics D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hex Call Locatio n RST 0 1 1 0 0 0 1 1 1 C 7 0000 RST 1 1 1 0 0 1 1 CF 0008 RST 2 1 1 0 1 1 1 D 7 0010 RST 3 1 1 0 1 1 1 DF 0018 RST 4 1 1 1 0 0 1 1 1 E 7 0020 RST 5 1 1 1 0 1 1 EF 0028 RST 6 1 1 0 1 1 1 F 7 0030 RST 7 1 1 1 1 FF 0038

Write a program to count continuously in binary with some delay between each Count. Service routine at 8070 H to flush FFH five times when the interrupt occurs (on INTR lines) with some appropriate delay between flash Main program Service routine LXI SP, FFFFH (stack region) EI MVI A, 00 H NXTCNT: OUT PORT 1 CALL DELAY (not defined here) INR A JMP NXTCNT PUSH B 8070: SERV: PUSH PSW MVI B, 0 AH MVI A, 00 H FLASH: OUT PORT 1 CALL DELAY CMA DCR B JNZ FLASH POP PSW POP B EI RET +5 V RST 5 code EF D 7 D 0 1 1 1 1 Inte rrup t instr : EF to data bus INTA from µP At 0028 H JMP 8070 H 0028 C 3 0029 70 002 A 80

Description • main program initializes stack pointer at FFFF and enables the interrupts. program will count continuously from 00 to FF with some delay between each count. • To interrupt the process, a switch at INTR us pushed. • the processor will complete the current instruction and senses the interrupt. Say the next instruction is INR A. • µP disables the interrupt flip-flop, and sends out INTA signal. • INTA enables the tri-state buffer and, and RST 5 (ie EF) is placed on the data bus. • µP saves the address of the INR A instruction on the stack at locations FFFE and FFFD, and the program is transferred to memory location 0028. The location 0028 has the JMP 8070 instruction to transfer the program to the service routine.

Description contd. • The program jumps to the service routine at 8070. • The service routing saves the registers that are being used in the subroutine and loads the count ten in register B to output five flashes and five blanks. • the service routine enables the interrupt before returning to main program. • When the service routine executes the RET instruction, the µP retrieves the address of the instruction INR A from the stack and continues the binary counting.

Short Questions • Ins there a minimum pulse width required for the INTR signal? – 17. 5 T states. CALL requir 18 T states. µP check INTR signal one clock period before the last T states. • How long can the INTR pulse stay high? – until the interrupt flip-flop is set by EI instruction in the subroutine. • Can the µP be interrupted again before the completion of the first interrupt service routine?

Vectored interrupts • TRAP, RST 7. 5, 6. 5 and 5. 5 do not require external instruction to jump to its call locations. these interrupts are called vectored interrupts. • maskable interrupts are enabled by two instructions: EI and SIM.

SIM • Set Interrupt Mask. 7 6 SOD SDE 5 XX 2 4 1 3 0 R 7. 5 MSE M 7. 5 M 6. 5 M 5. 5 0=available, 1=masked no use serial out data: ignored if bit 6 is 0 0 = ignore mask bits 1 = mask bits are enabled if 1, Reset 7. 5 if 1, bit 7 is serial data out Enabling all interrupts: EI ; enable interrupts MVI A, 08 h ; load bit patters for intr SIM ; Enables 7. 5, 6. 5, 5. 5

RIM • Read Interrupt Mask. – read to sense the pending interrupts. • RIM loads accumulator with 8 bits indicating status of the interrupt masks. • RIM can also be used to read serial data. 7 SID 6 I 7. 5 5 I 6. 5 4 I 5. 5 1 = pending 3 IE 2 1 0 M 7. 5 M 6. 5 M 5. 5 1 = masked 1 = Interrupt enabled Serial input data, if any

RIM example • Assuming the µP is completing an RST 7. 5 interrupt request, check to see if RST 6. 5 is pending. If it is pending, enable RST 6. 5 without affecting any other interrupts; otherwise return to main program. RIM ; Read interrupt mask MOV B, A ; save mask info ANI 20 h ; check if RST 6. 5 is pending JNZ NEXT ; EI RET ; RST 6. 5 is not pending; return to main program NEXT: MOV A, B ; get bit pattern; RST 6. 5 pending ANI 0 Dh ; enables RST 6. 5 by setting D 1=0 ORI 08 h ; enable SIM by setting D 3=1 SIM JMP SERV ; Jump service routing for RST 6. 5 at SERV

DMA • Direct Memory Access – IO device can transfer data from (to) memory directly. – When µP controlled data transfer is too slow • HOLD – an input high signal to this pin initiated DMA. µP releases bus in the following machine cycle. gets back the control when HOLD is low. • HLDA – HOLD Ackn. After releasing the bus µP sends a high signal at this pin to inform the IO device.

DMA contd. • Usually a DMA controller sends the DMA request to MP. The processor completes the current machine cycle; floats all the bus lines, and sends a ackn signal to HLDA. DMA controller takes the control of the buses and transfer data directly to memory from the external source by-passing µP. After data transfer DMA controller sends a low signal at HOLD pin to terminate the request for DMA. MP gets back its control over the buses. Address MPU Memory DMA contr oller IO control Data Bus HOLD HLDA

8086/8088 Architecture • • Seven categories of signals. Power & Max/min mode: min mode is used for clock single procss. Max mode is used for multiprocss Test: synchronize multiple processors Data Enable: generally connected to External rqst biriectional buffer to isolate MPU from system bus. Response to Data tran/rcvr: controls data flow. External rqst IO or memory: indicates whether the proc cycle is memory operation or IO Multipro operation. envrnmnt Bus High Enable: enble the higher order byte of 16 bit data VCC CLK GND INTR NMI HOLD READY RESET INTA HOLDA TEST MN/MX BHE/S 7 A 19/S 6 Mu. X add & status signals A 16/S 3 AD 15 AD 0 ALE M/IO RD WR DEN DT/R Mux add and data buses Control & status signals

Max/min mode control signals Pin Min mode Max mode 24 INTA QS 1: queue status signal 25 ALE QS 0: queue stat signal 26 DEN S 0: input sig to bus control 27 DT/R S 1: “ 28 M/IO S 2: “ 29 WR Lock: to prvnt another proc from gaining control 30 HLDA RQ/GT 1: enable another processor to gain control 31 HOLD RQ/GT 0: “

8086 Programming model

• segment registers work together with general purpose register to access any memory value. For example if we would like to access memory at the physical address 12345 h (hexadecimal), we should set the DS = 1230 h and SI = 0045 h. This is good, since this way we can access much more memory than with a single register that is limited to 16 bit values. CPU makes a calculation of physical address by multiplying the segment register by 10 h and adding general purpose register to it (1230 h * 10 h + 45 h = 12345 h): by default BX, SI and DI registers work with DS segment register; BP and SP work with SS segment register. Other general purpose registers cannot form an effective address! also, although BX can form an effective address, BH and BL cannot.

• special purpose registers – IP - the instruction pointer. – flags register - determines the current state of the microprocessor. • IP register always works together with CS segment register and it points to currently executing instruction.

Memory Access [BX + SI] [BX + DI] [BP + SI] [BP + DI] [SI] [DI] d 16 (variable offset only) [BX] [BX + SI + d 8] [BX + DI + d 8] [BP + SI + d 8] [BP + DI + d 8] [SI + d 8] [DI + d 8] [BP + d 8] [BX + SI + d 16] [BX + DI + d 16] [BP + SI + d 16] [BP + DI + d 16] [SI + d 16] [DI + d 16] [BP + d 16] [BX + d 16]

• for example, let's assume that DS = 100, BX = 30, SI = 70. The following addressing mode: [BX + SI] + 25 is calculated by processor to this physical address: 100 * 16 + 30 + 70 + 25 = 1725. by default DS segment register is used for all modes except those with BP register, for these SS segment register is used. there is an easy way to remember all those possible combinations using this chart: you can form all valid combinations by taking only one item from each column or skipping the column by not taking anything from it. as you see BX and BP never go together. SI and DI also don't go together. here an examples of a valid addressing modes: [BX+5] , [BX+SI] , [DI+BX-4]

80286 • 16 bit • Eliminates the multiplexing of buses. • Has 24 bit linear address bus support 16 M bytes address directly. • Supports memory management through which it can support 1 Gbytes of virtual memory. • Protects system software from user programs, protects users’ program, and restricts access to some memory regions. • Supports multiuser systems.

80386/486 • 32 bit processor. • Support following multiuser system requirement – – High speed of execution Ability to handle different types of tasks efficiently Large memory space that can be shared by multiuser Appropriate memory allocations and the management of memory access – Data security and data access – Limited and selected access to part of the system – Resource sharing and management

• 32 bit non-multiplexed address bus • Can address 4 G physical memory and through a memory management unit 64 (246) terabytes of virtual memory. • Two modes: real mode, and protected mode. • Execution is highly pipelined.

80386 Programming model • 8 -general purpose registers can be accessed as 8, 16 or 32 bit • 6 -segment selector registers. • IP can used as 16/32 bits • Flag is 31 bits but 14 are used at present. • 6 for data, 3 operation, 2 io previl, 1 nested task, 2 for VM 31 15 7 AX BX CX DX SP BP SI DI CS SS DS ES FS GS IP FLAGS 0

Temperature control

Internal architecture of 8085 ALU