The PFIT Project WW 0714 Intel Corporation Platform

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 The PFIT Project WW 07'14 Intel Corporation Platform Engineering Group Nick Klein Jan

The PFIT Project WW 07'14 Intel Corporation Platform Engineering Group Nick Klein Jan 30, 2014 1 INTEL CONFIDENTIAL

The PFIT Project Agenda • Objective • Strategy • Timeline 2 Intel and the

The PFIT Project Agenda • Objective • Strategy • Timeline 2 Intel and the Intel logo are trademarks of Intel Corporation the U. S. and other countries. Other names and brands may be claimed as the property of others. All products, dates, and figures are preliminary and are subject to change without any notice. Copyright © 2012, Intel Corporation. Reference Number: XXXXXX Intel Confidential Revision: 1. 0

The PFIT Project key objectives • Apply LEAN principles to Advanced FI • Define

The PFIT Project key objectives • Apply LEAN principles to Advanced FI • Define equipment required to optimize automated Advanced FI test throughput time (TPT) • Development of industry standard automated Advanced FI equipment to significantly reduce FI throughput time and expense. 3 Intel and the Intel logo are trademarks of Intel Corporation the U. S. and other countries. Other names and brands may be claimed as the property of others. All products, dates, and figures are preliminary and are subject to change without any notice. Copyright © 2012, Intel Corporation. Reference Number: XXXXXX Intel Confidential Revision: 1. 0

Reasons for the PFIT project • Advanced FI methodologies currently rely on equipment intended

Reasons for the PFIT project • Advanced FI methodologies currently rely on equipment intended for functional FI. • Functional and Advanced FI equipment needs differ significantly, in that testing is often performed on completely non-functional parts, and require much higher test currents and dual-polarity voltages. • This project extends the capability of Advanced FI across all product lines to significantly decrease TPT. 4 Intel and the Intel logo are trademarks of Intel Corporation the U. S. and other countries. Other names and brands may be claimed as the property of others. All products, dates, and figures are preliminary and are subject to change without any notice. Copyright © 2012, Intel Corporation. Reference Number: XXXXXX Intel Confidential Revision: 1. 0

The PFIT Project Agenda • Objective • Strategy • Timeline 5 Intel and the

The PFIT Project Agenda • Objective • Strategy • Timeline 5 Intel and the Intel logo are trademarks of Intel Corporation the U. S. and other countries. Other names and brands may be claimed as the property of others. All products, dates, and figures are preliminary and are subject to change without any notice. Copyright © 2012, Intel Corporation. Reference Number: XXXXXX Intel Confidential Revision: 1. 0

The PFIT Project strategy • Identify strategies to enhance existing functional FI • Determine

The PFIT Project strategy • Identify strategies to enhance existing functional FI • Determine essential minimum equipment • Curve tracing • Latch up • High-current Bin 8 Develop TIU • • Universal carrier interface • Daughter board per product Develop automated Lab. View test procedures • • • 6 Mostly universal across product lines Document entire system for copy-exact to other sites Intel and the Intel logo are trademarks of Intel Corporation the U. S. and other countries. Other names and brands may be claimed as the property of others. All products, dates, and figures are preliminary and are subject to change without any notice. Copyright © 2012, Intel Corporation. Reference Number: XXXXXX Intel Confidential Revision: 1. 0

The PFIT Project Agenda • Objective • Strategy • Timeline 7 Intel and the

The PFIT Project Agenda • Objective • Strategy • Timeline 7 Intel and the Intel logo are trademarks of Intel Corporation the U. S. and other countries. Other names and brands may be claimed as the property of others. All products, dates, and figures are preliminary and are subject to change without any notice. Copyright © 2012, Intel Corporation. Reference Number: XXXXXX Intel Confidential Revision: 1. 0

The PFIT Project timeline Phase 1 Q 1’ 14 Phase 2 Completion Q 2’

The PFIT Project timeline Phase 1 Q 1’ 14 Phase 2 Completion Q 2’ 14 Q 3’ 14 WW 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Spec writing Board design and Software Design Harness Design Pre-Power On testing. 8 Boards in house Demos and implementation Validation Intel and the Intel logo are trademarks of Intel Corporation the U. S. and other countries. Other names and brands may be claimed as the property of others. All products, dates, and figures are preliminary and are subject to change without any notice. Copyright © 2012, Intel Corporation. Reference Number: XXXXXX Intel Confidential Revision: 1. 0

9 Intel and the Intel logo are trademarks of Intel Corporation the U. S.

9 Intel and the Intel logo are trademarks of Intel Corporation the U. S. and other countries. Other names and brands may be claimed as the property of others. All products, dates, and figures are preliminary and are subject to change without any notice. Copyright © 2012, Intel Corporation. Reference Number: XXXXXX Intel Confidential Revision: 1. 0

Back up 10 Intel and the Intel logo are trademarks of Intel Corporation the

Back up 10 Intel and the Intel logo are trademarks of Intel Corporation the U. S. and other countries. Other names and brands may be claimed as the property of others. All products, dates, and figures are preliminary and are subject to change without any notice. Copyright © 2012, Intel Corporation. Reference Number: XXXXXX Intel Confidential Revision: 1. 0

Backplane block diagram 11 Intel and the Intel logo are trademarks of Intel Corporation

Backplane block diagram 11 Intel and the Intel logo are trademarks of Intel Corporation the U. S. and other countries. Other names and brands may be claimed as the property of others. All products, dates, and figures are preliminary and are subject to change without any notice. Copyright © 2012, Intel Corporation. Reference Number: XXXXXX Intel Confidential Revision: 1. 0

Family board block diagram 12 Intel and the Intel logo are trademarks of Intel

Family board block diagram 12 Intel and the Intel logo are trademarks of Intel Corporation the U. S. and other countries. Other names and brands may be claimed as the property of others. All products, dates, and figures are preliminary and are subject to change without any notice. Copyright © 2012, Intel Corporation. Reference Number: XXXXXX Intel Confidential Revision: 1. 0