Intel 8086 MICROPROCESSOR Architecture Features q It is








































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Intel 8086 MICROPROCESSOR Architecture

Features q It is a 16 -bit μp. q 8086 has a 20 bit address bus can access up to 220 memory locations (1 MB). q It can support up to 64 K I/O ports. q It provides 14, 16 -bit registers. q Word size is 16 bits. q It has multiplexed address and data bus AD 0 - AD 15 and A 16 – A 19. 2

8086 Microprocessor Architecture Execution Unit (EU) Bus Interface Unit (BIU) EU executes instructions that have already been fetched by the BIU fetches instructions, reads data from memory and I/O ports, writes data to memory and I/ O ports. BIU and EU functions separately. 3

8086 Microprocessor Architecture Bus Interface Unit (BIU) Dedicated Adder to generate 20 bit address Four 16 -bit segment registers Code Segment (CS) Data Segment (DS) Stack Segment (SS) Extra Segment (ES) Segment Registers >> 4

8086 Microprocessor Architecture Bus Interface Unit (BIU) Instruction queue A group of First-In-First. Out (FIFO) in which up to 6 bytes of instruction code are pre fetched from the memory ahead of time. This is done in order to speed up the execution by overlapping instruction fetch with execution. This mechanism is known as pipelining. 5

8086 Microprocessor Architecture Execution Unit (EU) EU decodes and executes instructions. A decoder in the EU control system translates instructions. 16 -bit ALU for performing arithmetic and logic operation Four general purpose registers(AX, BX, CX, DX); Pointer registers (Stack Pointer, Base Pointer); and Index registers (Source Index, Destination Index) each of 16 -bits Some of the 16 bit registers can be used as two 8 bit registers as : AX can be used as BX can be used as CX can be used as DX can be used as AH and AL BH and BL CH and CL DH and DL 6

Internal architecture of 8086 • 8086 has two blocks BIU and EU. • The BIU handles all transactions of data and addresses on the buses for EU. • The BIU performs all bus operations such as instruction fetching, reading and writing operands for memory and calculating the addresses of the memory operands. The instruction bytes are transferred to the instruction queue. • EU executes instructions from the instruction system byte queue. 7

• Both units operate asynchronously to give the 8086 an overlapping instruction fetch and execution mechanism which is called as Pipelining. This results in efficient use of the system bus and system performance. • BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder. • EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag register. 8

EXECUTION UNIT • Decodes instructions fetched by the BIU • Generate control signals, • Executes instructions. The main parts are: • Control Circuitry • Instruction decoder • ALU 9

THE QUEUE (Q) • The BIU uses a mechanism known as an instruction stream queue to implement a pipeline architecture. • This queue permits pre-fetch of up to 6 bytes of instruction code. Whenever the queue of the BIU is not full, it has room for at least two more bytes and at the same time the EU is not requesting it to read or write operands from memory, the BIU is free to look ahead in the program by pre-fetching the next sequential instruction. 10

• These pre-fetching instructions are held in its FIFO queue. With its 16 bit data bus, the BIU fetches two instruction bytes in a single memory cycle. • After a byte is loaded at the input end of the queue, it automatically shifts up through the FIFO to the empty location nearest the output. • The EU accesses the queue from the output end. It reads one instruction byte after the other from the output of the queue. • The intervals of no bus activity, which may occur between bus cycles are known as Idle state. 11

Segment: Offset Notation • The total addressable memory size is 1 MB • Most of the processor instructions use 16 -bit pointers the processor can effectively address only 64 KB of memory • To access memory outside of 64 KB the CPU uses special segment registers to specify where the code, stack and data 64 KB segments are positioned within 1 MB of memory

Segment: Offset Notation • A simple scheme would be to order the bytes in a serial fashion and number them from 0 (or 1) to the end of memory • The scheme used in the 8086 is called segmentation • Every address has two parts, a SEGMENT and an OFFSET (Segmnet: Offset ) • The segment indicates the starting of a 64 kilobyte portion of memory, in multiples of 16 • The offset indicates the position within the 64 k portion • Absolute address = (segment * 16) + offset

Segment registers • In 8086/88 the processors have 4 segments registers • Code Segment register (CS), Data Segment register (DS), Extra Segment register (ES) and Stack Segment (SS) register. • All are 16 bit registers. • Each of the Segment registers store the upper 16 bit address of the starting address of the corresponding segments. 14

Physical Memory Segmented Memory 0000 0 §The memory in an 8086/88 based system is organized as segmented memory. Code segment (64 KB) Data segment (64 KB) 1 MB §The CPU 8086 is able to address 1 Mbyte of memory. Extra segment (64 KB) §The Complete physically available memory may be divided into a number of logical segments. Stack segment (64 KB) FFFFF 15

• The size of each segment is 64 KB • A segment is an area that begins at any location which is divisible by 16. • A segment may be located any where in the memory • Each of these segments can be used for a specific function. – Code segment is used for storing the instructions. – The stack segment is used as a stack and it is used to store the return addresses. – The data and extra segments are used for storing data byte. * In the assembly language programming, more than one data/ code/ stack segments can be defined. But only one segment of each type can be accessed at any time. 16

MEMORY BI U CSR 0000 0 Segment Registers 34 BA 44 EB ESR 54 EB SSR 44 EB 0 54 EAF 54 EB 0 CODE (64 k) DATA (64 K) 1 MB DSR 34 BA 0 44 B 9 F EXTRA (64 K) 64 EAF 695 E 0 795 D F Each segment register store the upper 16 bit of the starting address of the segments STACK (64 K) 17

8086 Microprocessor Segment Registers Architecture Bus Interface Unit (BIU) Code Segment Register 16 -bit CS contains the base or start of the current code segment; IP contains the distance or offset from this address to the next instruction byte to be fetched. BIU computes the 20 -bit physical address by logically shifting the contents of CS 4 -bits to the left and then adding the 16 -bit contents of IP. That is, all instructions of a program are relative to the contents of the CS register multiplied by 16 and then offset is added provided by the IP. 18

8086 Microprocessor Segment Registers Architecture Bus Interface Unit (BIU) Data Segment Register 16 -bit Points to the current data segment; operands for most instructions are fetched from this segment. The 16 -bit contents of the Source Index (SI) or Destination Index (DI) or a 16 -bit displacement are used as offset for computing the 20 -bit physical address. 19

8086 Microprocessor Segment Registers Architecture Bus Interface Unit (BIU) Stack Segment Register 16 -bit Points to the current stack. The 20 -bit physical stack address is calculated from the Stack Segment (SS) and the Stack Pointer (SP) for stack instructions such as PUSH and POP. In based addressing mode, the 20 -bit physical stack address is calculated from the Stack segment (SS) and the Base Pointer (BP). 20

8086 Microprocessor Segment Registers Architecture Bus Interface Unit (BIU) Extra Segment Register 16 -bit Points to the extra segment in which data (in excess of 64 K pointed to by the DS) is stored. String instructions use the ES and DI to determine the 20 bit physical address for the destination. 21

8086 Microprocessor Segment Registers Architecture Bus Interface Unit (BIU) Instruction Pointer 16 -bit Always points to the next instruction to be executed within the currently executing code segment. So, this register contains the 16 -bit offset address pointing to the next instruction code within the 64 Kb of the code segment area. Its content is automatically incremented as the execution of the next instruction takes place. 22

Instruction pointer & summing block • The instruction pointer register contains a 16 -bit offset address of instruction that is to be executed next. • The IP always references the Code segment register (CS). • The value contained in the instruction pointer is called as an offset because this value must be added to the base address of the code segment, which is available in the CS register to find the 20 -bit physical address. • The value of the instruction pointer is incremented after executing every instruction. • To form a 20 bit address of the next instruction, the 16 bit address of the IP is added (by the address summing block) to the address contained in the CS , which has been shifted four bits to the left. 23

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• The following examples shows the CS: IP scheme of address formation: IP 8 AB 4 CS 34 BA Inserting a hexadecimal 0 H (0000 B) 34 BA 0 Code segment 8 AB 4 with the CSR or shifting the CSR (offset) four binary digits left 3 D 64 5 34 BA 0(CS)+ 8 AB 4(IP) 3 D 65 4 (next address) 44 B 9 F 25

Q. 2 A memory location has physical address 80 FD 2 h. In what segment does it have offset BFD 2 h? Solution: physical address= segment. X 10 h+offset Physical address =80 FD 2 h -offset = BFD 2 h Segment X 10 h= 75000 h 26

Q. 1. For the memory locations whose physical address is specified by 1256 Ah, give the address in segment: offset form for segments 1256 h and 1240 h. Solution: let X be the offset in segment 1256 h and Y the offset in segment 1240 h. We have 1256 A=12560 h+X and 1256 Ah=12400 h+Y X =1256 Ah-12560 h and Y=1256 Ah-12400 h Ah 16 Ah 1256 Ah=1256: 000 A=1240: 016 A 27

• Example For Address Calculation (segment: offset) • If the data segment starts at location 1000 h and a data reference contains the address 29 h where is the actual data? Offset Segment Address Required Address 0000 0010 1001 0000 0001 0000 0010 1001 28

Segment and Address register combination • CS: IP • SS: SP SS: BP • DS: BX DS: SI • DS: DI (for other than string operations) • ES: DI (for string operations) 29

8086 Microprocessor EU Registers Architecture Execution Unit (EU) Accumulator Register (AX) Consists of two 8 -bit registers AL and AH, which can be combined together and used as a 16 -bit register AX. AL in this case contains the low order byte of the word, and AH contains the high-order byte. The I/O instructions use the AX or AL for inputting / outputting 16 or 8 bit data to or from an I/O port. Multiplication and Division instructions also use the AX or AL. 30

8086 Microprocessor EU Registers Architecture Execution Unit (EU) Base Register (BX) Consists of two 8 -bit registers BL and BH, which can be combined together and used as a 16 -bit register BX. BL in this case contains the low-order byte of the word, and BH contains the high-order byte. This is the only general purpose register whose contents can be used for addressing the 8086 memory. All memory references utilizing this register content for addressing use DS as the default segment register. 31

8086 Microprocessor EU Registers Architecture Execution Unit (EU) Counter Register (CX) Consists of two 8 -bit registers CL and CH, which can be combined together and used as a 16 -bit register CX. When combined, CL register contains the low order byte of the word, and CH contains the high-order byte. Instructions such as SHIFT, ROTATE and LOOP use the contents of CX as a counter. Example: The instruction LOOP START automatically decrements CX by 1 without affecting flags and will check if [CX] = 0. If it is zero, 8086 executes the next instruction; otherwise the 8086 branches to the label START. 32

8086 Microprocessor EU Registers Architecture Execution Unit (EU) 33

8086 Microprocessor EU Registers Architecture Execution Unit (EU) Stack Pointer (SP) and Base Pointer (BP) SP and BP are used to access data in the stack segment. SP is used as an offset from the current SS during execution of instructions that involve the stack segment in the external memory. SP contents are automatically updated (incremented/ decremented) due to execution of a POP or PUSH instruction. BP contains an offset address in the current SS, which is used by instructions utilizing the based addressing mode. 34

8086 Microprocessor EU Registers Architecture Execution Unit (EU) Source Index (SI) and Destination Index (DI) Used in indexed addressing. Instructions that process data strings use the SI and DI registers together with DS and ES respectively in order to distinguish between the source and destination addresses. 35

8086 Microprocessor EU Registers Architecture Execution Unit (EU) Source Index (SI) and Destination Index (DI) Used in indexed addressing. Instructions that process data strings use the SI and DI registers together with DS and ES respectively in order to distinguish between the source and destination addresses. 36

EXECUTION UNIT – Flag Register • A flag is a flip flop which indicates some conditions produced by the execution of an instruction or controls certain operations of the EU. • In 8086 The EU contains a 16 bit flag register 9 of the 16 are active flags and remaining 7 are undefined. 6 flags indicates some conditions- status flags 3 flags –control Flags U U Over flow U U OF DF IF Direction U - Unused TF SF ZF U Interrupt Trap Sign AF U PF U Auxiliary Zero Parity CF Carry 37

8086 Microprocessor Execution Unit (EU) Architecture Auxiliary Carry Flag Register Carry Flag This is set, if there is a carry from the lowest nibble, i. e, bit three during addition, or borrow for the lowest nibble, i. e, bit three, during subtraction. This flag is set, when there is a carry out of MSB in case of addition or a borrow in case of subtraction. Sign Flag Zero Flag Parity Flag This flag is set, when the result of any computation is negative This flag is set, if the result of the computation or comparison performed by an instruction is zero This flag is set to 1, if the lower byte of the result contains even number of 1’s ; for odd number of 1’s set to zero. 15 14 13 12 11 10 9 8 7 6 OF DF IF TF SF ZF 5 Over flow Flag This flag is set, if an overflow occurs, i. e, if the result of a signed operation is large enough to accommodate in a destination register. The result is of more than 7 -bits in size in case of 8 -bit signed operation and more than 15 -bits in size in case of 16 -bit sign operations, then the overflow will be set. Direction Flag This is used by string manipulation instructions. If this flag bit is ‘ 0’, the string is processed beginning from the lowest address to the highest address, i. e. , auto incrementing mode. Otherwise, the string is processed from the highest address towards the lowest address, i. e. , auto incrementing mode. 4 AF 3 2 PF 1 0 CF Tarp Flag If this flag is set, the processor enters the single step execution mode by generating internal interrupts after the execution of each instruction Interrupt Flag Causes the 8086 to recognize external mask interrupts; clearing IF disables these interrupts. 38

8086 Microprocessor Architecture 8086 registers categorized into 4 groups 15 Sl. No. Type 1 General purpose register 14 13 12 11 10 9 8 7 6 OF DF IF TF SF ZF Register width 5 4 3 AF 2 1 PF CF Name of register 16 bit AX, BX, CX, DX 8 bit AL, AH, BL, BH, CL, CH, DL, DH 2 Pointer register 16 bit SP, BP 3 Index register 16 bit SI, DI 4 Instruction Pointer 16 bit IP 5 Segment register 16 bit CS, DS, SS, ES 6 Flag (PSW) 16 bit Flag register 0 39

8086 Microprocessor Register Architecture Name of the Registers and Special Functions Special Function AX 16 -bit Accumulator Stores the 16 -bit results of arithmetic and logic operations AL 8 -bit Accumulator Stores the 8 -bit results of arithmetic and logic operations BX Base register Used to hold base value in base addressing mode to access memory data CX Count Register Used to hold the count value in SHIFT, ROTATE and LOOP instructions DX Data Register Used to hold data for multiplication and division operations SP Stack Pointer Used to hold the offset address of top stack memory BP Base Pointer Used to hold the base value in base addressing using SS register to access data from stack memory SI Source Index Used to hold index value of source operand (data) for string instructions DI Data Index Used to hold the index value of destination operand (data) for string operations 40
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