Microprocessors 1 MCS51 Interrupts Microprocessors 1 Msc Ivan

Microprocessors 1 MCS-51 Interrupts Microprocessors 1 Msc. Ivan A. Escobar 1

Interrupts • An interrupt is the occurrence of an event that causes a temporary suspension of a program while the condition is serviced by another program. – Allow a system to respond asynchronously to an event and deal with the event while another program is executing. • An interrupt driven system gives the illusion of doing many things simultaneously. – Of course, the CPU cannot execute more than one instruction at a time. • It can temporarily suspend execution of one program, execute another, then return to the first program. – In a way, interrupts are like subroutines. Except that one does not know when the interrupt code will be executed. Microprocessors 1 Msc. Ivan A. Escobar 2

Example • An embedded system is controlling a Microwave oven. – The main program is controlling the power element of the oven. – The use presses a key on the front panel to cancel the operation or change the length of cooking time. – The main program is interrupted. The ISR takes over, reads the keypad and changes the cooking conditions accordingly, then finishes by passing control back to the main program. – The main program continues according to the new conditions set by the ISR. • The important aspect is that the keypad entry occurs asynchronously with respect to the main program. – The main program cannot anticipate when the key will be pressed. Microprocessors 1 Msc. Ivan A. Escobar 3

Interrupts vs. Polling • Polling: – CPU monitors all served devices continuously, looking for a “service request flag” – Whenever it sees a request, it serves the device and then keeps polling – CPU is always “busy” with polling doing the “while any request” loop • Interrupts – If and when a device is ready and needs attention, it informs the CPU – CPU drops whatever it was doing and serves the device and then returns back to its original task – CPU is always “free”, when not serving any interrupts Microprocessors 1 Msc. Ivan A. Escobar 4

Interrupt Service Routines • • CPUs have fixed number of interrupts – Every interrupt has to be associated with a piece of code called “Interrupt Service Routine”, or ISR. – If interrupt-x is received by CPU, the ISR-x is executed CPU architecture defines a specific “code address” for each ISR, which is stored in the, – “Interrupt vector Table (IVT)” ISRs are basically “subroutines”, but they end with the RETI, instruction instead of RET When an interrupt occurs, the CPU fetches its ISR code address from the IVT and executes it. Microprocessors 1 Msc. Ivan A. Escobar 5

Interrupt Execution 1. 2. 3. 4. 5. CPU finishes the instruction it is currently executing and stores the PC on the stack CPU saves the current status of all interrupts internally Fetches the ISR address for the interrupt from IVT and jumps to that address Executes the ISR until it reaches the RETI instruction Upon RETI, the CPU pops back the old PC from the stack and continues with whatever it was doing before the interrupt occurred Microprocessors 1 Msc. Ivan A. Escobar 6

MCS-51 Interrupts • There are 5 interrupts in the 8051. – Clones may differ. – Two external interrupts (INT 0 and INT 1), two timer interrupts (TF 0 and TF 1) and one serial port interrupt (SI). • Interrupts can be individually enabled or disabled. This is done in the IE (Interrupt Enable) register (A 8 H). – IE is bit addressable. • All interrupts correspond to bits in registers. – Therefore, it is possible to cause an interrupt by setting the appropriate bit in the appropriate register. • The end result is exactly as if the hardware interrupt occurred. Microprocessors 1 Msc. Ivan A. Escobar 7

The IE Register MSB LSB EA Bit • • - ET 2 ES ET 1 EX 1 ET 0 EX 0 Name Description IE. 7 EA Enable/Disable all interrupts If 0 all interrupts are disabled. If 1, interrupts are enabled based on their individual bits IE. 6 - Reserved IE. 5 ET 2 Enable/Disable Timer 2 interrupt (8052) IE. 4 ES Enable/Disable Serial Input Interrupt IE. 3 ET 1 Enable/Disable Timer 1 Interrupt (TF 1) IE. 2 EX 1 Enable/Disable External Interrupt 1 (INT 1) IE. 1 ET 0 Enable/Disable Timer 0 Interrupt (TF 0) IE. 0 EX 0 Enable/Disable External Interrupt 0 (INT 0) Putting a 1 in a bit enables its interrupt. Putting a 0 masks that interrupt. Microprocessors 1 Msc. Ivan A. Escobar 8

Interrupt Priority • The 8051 implements 2 types of interrupt priority. • User Defined Priority. – Using the IP register, the user can group interrupts into two levels – high and low. • An interrupt is assigned a “high” priority level by setting its bit in the IP register to 1. If the bit is set to 0, the interrupt gets a “low” priority. • Automatic Priority. – Within each priority level, a strict order is observed. • Interrupts are ordered as follows: INT 0, TF 0, INT 1, TF 1, SO. Microprocessors 1 Msc. Ivan A. Escobar 9

The IP Register MSB LSB - Bit • - PT 2 PS PT 1 PX 1 Name Description IP. 7 - Reserved IP. 6 - Reserved IP. 5 ET 2 Timer 2 interrupt priority (8052) IP. 4 ES Serial Port Interrupt priority IP. 3 ET 1 Timer 1 Interrupt priority (TF 1) IP. 2 EX 1 External Interrupt 1 priority (INT 1) IP. 1 ET 0 Timer 0 Interrupt priority (TF 0) IP. 0 EX 0 External Interrupt 0 priority (INT 0) PT 0 PX 0 Putting a 1 in a bit assigns its interrupt to the high priority level. Microprocessors 1 Msc. Ivan A. Escobar 10

Pending Interrupts • If an interrupt occurs while it is disabled, or while a higher priority interrupt is active, it becomes pending. – As soon as the interrupt is enabled, it will cause a call. – It is also possible to cancel it by software by clearing the appropriate bit in the register. Microprocessors 1 Msc. Ivan A. Escobar 11

Response Time • Response time is the amount of time between the occurrence of the interrupt event and the start of execution of the service routine. • For the MCS-51, the shortest possible response time is 3 machine cycles and the longest is 9. • Interrupts are not recognized during specific instructions. An additional instruction must complete before interrupts will be recognized. – RETI and any instruction that modifies the contents of IE or IP. Microprocessors 1 Msc. Ivan A. Escobar 12

Activation Levels – INT 0 and INT 1 • The activation for INT 0 and INT 1 can be configured to be level-triggered or edge-triggered based on bits IT 0 and IT 1 in the TCON register MSB TF 1 LSB TR 1 TF 0 TR 0 IE 1 IT 1 IE 0 IT 0 – For level-triggered (ITx = 0, default), a low on the pin causes an interrupt. – For edge-triggered (ITx = 1), a high-to-low transition causes the interrupt. Microprocessors 1 Msc. Ivan A. Escobar 13

INT 0 and INT 1 (Contd. ) • If INTx is configured as edge-triggered, then the change in value of the flag bit IEx in the TCON register is what causes the interrupt. – It can be forced through software. • If it is configured as level-triggered, then the interrupting device is what controls the value of the flag. • The flag will be automatically cleared at the end of the ISR. – After the RETI. • Prevents interrupts of the same type within an interrupt. Microprocessors 1 Msc. Ivan A. Escobar 14

Activation Levels – TF 0 and TF 1 • The TF 0 and TF 1 interrupts are essentially edgetriggered. – The interrupt occurs when the counter goes from FFFFH to 0000 H. • The flag goes from low to high. • These flags will be automatically cleared when the ISR is started. Microprocessors 1 Msc. Ivan A. Escobar 15

MCS-51 IVT Microprocessors 1 Symbol Address Interrupt Source RESET 00 H Power Up or Reset EXTI 0 03 H External Interrupt 0 TIMER 0 0 BH Timer 0 Interrupt EXTI 1 13 H External Interrupt 1 TIMER 1 1 BH Timer 1 Interrupt SINT 23 H Serial Port Interrupt Msc. Ivan A. Escobar 16