INTRODUCING Enhanced 8 bit MidRange PIC Microcontroller MCU

INTRODUCING: Enhanced 8 -bit Mid-Range PIC® Microcontroller (MCU) Core Detailed Technical Overview

Agenda l Introducing the PIC 16 F 1 XXX l Migration to the PIC 16 F 1 XXX l New Coding Tricks l Advanced Capabilities 2

Introducing the PIC 16 F 1 XXX

Introducing the PIC 16 F 1 XXX l Overview l Memory Map l New Instructions l Enhanced Indirect Memory Features 4

PIC® Microcontroller Family Roadmap Memory/Performance PIC 32 ds. PIC® DSC PIC 24 PIC 18 (16 -bit instruction word) Enhanced PIC 16 (14 -bit instruction word) PIC 10/12 (12 -bit instruction word) Price 5

PIC 16 Enhancement GOALS l Increase maximum program memory l Increase space for peripherals l Increase maximum data memory Maintain 14 -bit program memory, Reduce penalty for paging/banking Improving ‘C’ efficiency to keep cost low l l l Minimize difficulty of migration 6

Front Page Comparison of PIC 16 XXX and PIC 16 F 1 XXX OLD NEW High-Performance RISC CPU: Only 35 instructions All single-cycle instructions except branches Only 49 instructions All single-cycle instructions except branches Operating speed: DC – 20 MHz oscillator/clock input DC – 200 ns instruction cycle Operating speed: DC – 32 MHz oscillator/clock input DC – 125 ns instruction cycle Interrupt capability with automatic context saving 8 -level-deep hardware stack 16 -level-deep hardware stack with Overflow/Underflow Reset Direct, Indirect and Relative Addressing modes Two full 16 -bit File Select Registers (FSRs) read program and data memory 7

Quick Comparison PIC 16 Max GPR/SFR 336 / 110 Enhanced PIC 16 2496 / 316 PIC 18 4096/159+ more, if the SFRs are outside of the access bank. Max Program 8 Kx 14 32 Kx 14 1 Mx 16 16 K is likely the largest device FSRs 1 2 3 can access program memory Instruction Count 35 Stack 8 Interrupts Program Memory Read 49 75 83 including the optional extended instructions 1 All devices via RETLW. Some devices via EEPROM interface 16 31 with over/underflow Reset 1 2 hardware context save optional hardware context save All devices via RETLW or FSR. All devices via EEPROM interface. All devices via TABLRD instructions. 8

New Data Memory Map l 32 Banks of File Registers - l The Memory Map is Simplified - l 15 banks are reserved for the future Bottom 16 bytes of each bank are common First 12 bytes of each bank are for the CPU registers SFRs are located at address 12 -31 New Features - W is mapped to “w reg” Banks 16 -30 are reserved for future fun Bank 31 has advanced functions 9

Data Memory Map Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 31 0 x 000 12 Common CORE SFRs 20 SFRs 20 Bank 31 6 - Stack Access and Debugging Registers Ba GPR GPR GPR 80 Bytes 80 Bytes 30 Special Functions s 0 x 01 F 0 x 020 SFRs 20 nk 0 x 00 B 0 x 00 C 0 x 06 F 0 x 070 Common Memory (16 bytes) 0 x 07 F 10

Common Core Registers NEW NEW Address Register Function 0 x 00 0 x 01 0 x 02 0 x 03 0 x 04 0 x 05 0 x 06 0 x 07 0 x 08 0 x 09 INDF 0 INDF 1 PCL STATUS FSR 0 Low FSR 0 High FSR 1 Low FSR 1 High BSR WREG Indirect Register 0 Indirect Register 1 Program Counter Low Status Register File Select Register 0 Low Byte File Select Register 0 High Byte File Select Register 1 Low Byte File Select Register 1 High Byte Bank Select Register Working Register 0 x 0 A PCLATH Program Counter Latch High 0 x 0 B INTCON Interrupt Control Register 11

Data Memory Banking l The old device required banking via RP 0 and RP 1 in the Status Register. l These bits NO LONGER EXIST. l Now the BSR register handles all banking. l The new MOVLB instruction selects the bank in one instruction. OLD IRP RP 1 RP 0 TO PD Z DC C 00 01 10 11 NEW STATUS - - - BSR - - - TO PD Z DC C 4 3 0 1 2 3 4 2 1 0 31 12

Program Memory l Program Memory Extended to 16 Pages of 2 Kbytes l Paging Simplified with MOVLP Instruction 6 5 4 3 2 1 0 MOVLP PCLATH - PCL 14 - 13 - 12 11 10 9 8 7 6 5 4 3 2 1 0 GOTO/CALL 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Program Counter 13

New FSR l l l 0 x 0000 2 x 16 -bit FSRs Access All File Registers and All Program Memory New FSRs Allow 1 Data Pointer for All Memory FSRs Are Now Supported By New Instructions FSR Addresses 0 x 0 FFF 0 x 1000 0 x 1 FFF 0 x 2000 0 x 29 FF 0 x 3 A 00 0 x 7 FFF 0 x 8000 0 x 0000 SFRs and GPRs BSR + File Register Addresses 0 x 0 FFF RESERVED Linear GPR Region RESERVED R ea FS ch R abl on e ly by l 0 x 0000 FSR MSb is set FSR Addresses 0 x. FFFF PROGRAM MEMORY Program Counter Addresses 0 x 7 FFF 14

Linear GPR Region BANK 0 GPR 80 Bytes l l Shadows 80 byte GPR blocks into linear array Keeps FSR operations inside GPR area Allows large stacks, arrays, buffers, etc. Access is via the FSR and a second address range 0 x 2000 BANK 0 0 x 204 F BANK 1 GPR 80 Bytes BANK 2 GPR 80 Bytes 12 Common CORE SFRs 20 SFRs 20 20 BANK 1 0 x 20 A 0 nk s FSR 0 x 20 EF Addresses BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 0 x 20 F 0 5 Bank 31 Ba GPR GPR GPR 0 x 213 F 80 Bytes 80 Bytes 0 x 2140 Common Memory (16 0 x 218 F 0 x 2190 bytes) 0 x 21 DF BANK 2 Special 630 SFRs 20 0 x 2050 SFRs 0 x 209 F BANK 3 GPR 80 Bytes Functions Stack Access and BANK Debugging 3 Registers BANK 4 GPR 80 Bytes BANK 5 GPR 80 Bytes 16

Fast Context Save l Interrupts automatically save the context - W STATUS BSR FSRs PCLATH l RETFIE automatically restores the context l You cannot disable fast context save 17

Stack l l l 16 Stack Entries Over/Underflow Reset (optional) User/ICD Stack Access in Bank 31 - Read/Write the Stack in Bank 31 ▪ Useful for RTOS or Safety Critical Debugging 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 18

Stack Reset Mode l The STRVEN (Stack Reset Violation Enable) Config bit enables the Stack Reset mode l Stack Reset Mode causes: - Return when stack is empty Call or interrupt when stack is full Reading the top of stack when stack is empty returns 0 19

Normal Mode l The stack works exactly as the legacy device, plus the following features l 16 -entry stack l Stack access via STKPTR and TOSH/TOSL 20

New Instructions Mnemonic Description ADDWFC SUBWFB LSLF LSRF ASRF MOVLP MOVLB BRA BRW CALLW ADDFSR MOVIW MOVWI RESET Add W+F with Carry Subtract F-W with Borrow Logical Shift Left Logical Shift Right Arithmetic Shift Right Move Literal to PCLATH Move Literal to BSR Branch Relative (signed) Branch PC + W (unsigned) Call PCLATH: W Add Literal to FSRn (signed) Move Indirect to W Move W to Indirect Reset Hardware and Software 21

Arithmetic with Carry l ADDWFC - l SUBWFB - l l Add with Carry Subtract with Borrow Literal Operations with Carry or Borrow Are Not Supported Original Add and Subtract Operations Still Available - Existing algorithms will still work! 22

Shift Instructions l ASRF - Arithmetic Right Shift l LSRF - Logical Right Shift l LSLF - Logical Left Shift - (This is the same as Arithmetic Shift Left. ) 23

Shift Instructions l ASRF - Arithmetic Right Shift REGISTERx 0 1 0 X 7 F 16 1 1 1 CARRY BIT 24

Shift Instructions l ASRF - Arithmetic Right Shift REGISTERx 0 0 1 1 0 X 3 F 16 1 1 CARRY BIT 1 MSB Duplicated 25

Shift Instructions l ASRF - Arithmetic Right Shift REGISTERx 1 0 0 X 8016 0 0 0 CARRY BIT 26

Shift Instructions l ASRF - Arithmetic Right Shift REGISTERx 1 1 0 0 0 XC 016 0 0 CARRY BIT 0 MSB Duplicated 27

Shift Instructions l LSRF - Logical Right Shift REGISTERx 0 1 0 X 7 F 16 1 1 1 CARRY BIT 28

Shift Instructions l LSRF - Logical Right Shift REGISTERx 0 0 1 1 0 X 3 F 16 ZERO SHIFTED IN 1 1 CARRY BIT 1 29

Shift Instructions l LSRF - Logical Right Shift REGISTERx 1 0 0 X 8016 0 0 0 CARRY BIT 30

Shift Instructions l LSRF - Logical Right Shift REGISTERx 0 1 0 0 0 X 3 F 16 ZERO SHIFTED IN 0 0 CARRY BIT 0 31

Shift Instructions l LSLF - Logical Left Shift REGISTERx 0 1 0 X 7 F 16 1 1 1 CARRY BIT 32

Shift Instructions l LSLF - Logical Left Shift ZERO SHIFTED IN REGISTERx 1 1 0 XFE 16 1 1 1 0 CARRY BIT 0 33

Shift Instructions l LSLF - Logical Left Shift REGISTERx 1 0 0 X 8016 0 0 0 CARRY BIT 34

Shift Instructions l LSLF - Logical Left Shift ZERO SHIFTED IN REGISTERx 0 0 0 X 0016 0 0 0 CARRY BIT 1 35

Paging/Banking l l MOVLP - Places 7 -bit literal in PCLATH MOVLP HIGH LABEL - PAGESEL in 1 cycle MOVLP + CALL/GOTO takes 3 cycles and 2 instructions, but reaches ANYWHERE in memory MOVLB - Places 5 -bit literal in BSR. BANKSEL in 1 cycle for ANY number of banks IRP, RP 0, RP 1 are obsolete and have been removed 36

Relative Branching l l Relative Branching allows MOST code to eliminate the paging concerns. BRA N (Branch Relative) - l BRW (Branch Relative with W) - l Always branch to PC + N Range is -256 <= N <= 255 PC + N is 15 -bit math, so no paging issues Always branch to PC + W (unsigned) Fast Lookup Tables/State Machines PC + W is 15 -bit math, so no paging issues CALLW (Call Absolute with W) - Call to PCLATH, W Fast Lookup Tables/State Machines/Function Pointers PCLATH: W direct address 37

FSR Support Instructions l ADDFSR instruction - Adds a signed literal to the selected FSR - Literal range is -32 to +31 l MOVIW/MOVWI – Move Indirect to W and Move W to Indirect - Special Modes ▪ ▪ ▪ Pre/Post-Increment Pre/Post-Decrement Relative Offset l Same range as ADDFSR 38

MOVIW/MOVWI Syntax l Standard l MOVIW --INDF 0 MOVWI 0[INDF 0] l Pre Increment MOVIW ++INDF 0 l Post Increment MOVWI INDF 0++ Modifies FSR Pre Decrement l Post Decrement MOVWI INDF 0 -- l Offset MOVWI k[INDF 0] -32 <= k <= 310 Does not modify FSR 39

Misc. Features l RESET instruction - No more GOTO 0 - All peripherals are reset - Software version of MCLR Reset - Another PCON bit is available to indicate a software Reset l Program Memory Read (PMR) is in every device. - Full 14 -bit read of program memory for check summing l Device ID, User ID and Config Word are now readable by the firmware. - User ID can be used for a serial number 40

Migration to the PIC 16 F 1 XXX

Migration l Paging l Banking l Interrupts l Indirect Memory 42

Paging l Use the PAGESEL macro - Automatically uses MOVLP OR l Update all PCLATH code - Assure 7 -bit data in PCLATH l Convert to relative branches - This will eliminate most paging issues. 43

PAGESEL My ASSEMBLY Code PAGESEL MACRO PIC 16 PAGESEL MACRO ENHANCED PIC 16 My_Function movlw 0 x 04 movwf delay_cntr My_function_loop decfsz delay_cntr goto My_function_loop return Maintains Portability Main do lots of stuff PAGESEL My_Function bsf PCLATH, 5 movlp high My_Function call My_Function bcf PCLATH, 4 call My_Function do lots of other stuff end end 44

Banking l Use BANKSEL macro, - Automatically uses MOVLB OR l Replace writes to STATUS with writes to BSR 45

BANKSEL My ASSEMBLY Code data Var 1 res 1 Var 2 res 1 Var 3 res 1 code Always works Main do lots of stuff BANKSEL Var 1 addwf Var 1 do lots of other stuff end BANKSEL MACRO PIC 16 data Var 1 res 1 Var 2 res 1 Var 3 res 1 code Main do lots of stuff bsf STATUS, RP 0 bcf STATUS, RP 1 addwf Var 1 do lots of other stuff end BANKSEL MACRO ENHANCED PIC 16 data Var 1 res 1 Var 2 res 1 Saves 1 instruction Var 3 res 1 and accesses code more banks of memory Main do lots of stuff movlb Var 1 >> 7 addwf Var 1 do lots of other stuff end 46

Interrupts l l RETFIE works a little differently 0 x 02 0 x 03 0 x 04 0 x 05 0 x 06 0 x 07 0 x 08 0 x 09 PCL STATUS FSR 0 Low FSR 0 High FSR 1 Low FSR 1 High BSR WREG Program Counter Low Status Register File Select Register 0 Low Byte File Select Register 0 High Byte File Select Register 1 Low Byte File Select Register 1 High Byte Bank Select Register Working Register Interrupts should not pass parameters with W (bad practice) - W will be restored! l Remove core context save/restore 0 x 0 A PCLATH Program Counter Latch High software 47

Indirect Memory l IRP bit is gone l Accessing > 256 bytes requires an update to FSRx. H Register l Fastest Method Update FSRx. H Register - l Requires modifying W For example, MOVLW and MOVWF BANKISEL is Portable - Performs 8 bcf’s or bsf’s (e. g. , 8 TCY) Does not preserve W 48

Migration Summary l Migrating to the PIC 16 F 1 xxx should be simple. l Using the BANKSEL and PAGESEL macros will be a big help. 49

New Coding Tricks

New Code Tricks l Relative Branching l Table Reads l 16 -bit Arithmetic l Robust Techniques 51

Relative Branches NEW ASSEMBLY ENHANCED PIC 16 ORIGINAL ASSEMBLY Code Additional Code My_Function movlw 0 x 04 movwf delay_cntr My_function_loop Page Boundary at this point will force the need for a PAGESEL Before My_function_loop My_Function movlw 0 x 04 movwf delay_cntr My_function_loop decfsz delay_cntr goto My_function_loop bra My_function_loop return Relative branch makes this code ALWAYS work with no paging issues. No relative CALL support. do lots of stuff CALLW is not relative. PAGESEL My_Function Main do lots of stuff PAGESEL call My_Function do lots of other stuff end 52

Table Reads l The PIC 16 F 1 XXX Has New ROM Table Access Methods - FSR - Relative Branch 53

Tables using FSR l Long setup The_CODE movlw high Table_start movwf FSR 0 H movlw low Table_start movwf FSR 0 L movlw 3 addwf FSR 0 L movf INDF 0, w Table_start DT 3, 4, 5, 6, 7, 8, 9 54

Fast Call Tables l This code returns a constant from a table aligned on a 256 word boundary The_CODE movlw 3 call Table_Function movwf movlw temp high Table_start movwf PCLATH movf temp, w movwf PCL The_CODE movlw 3 movlp high Table_start callw Table_start DT 3, 4, 5, 6, 7, 8, 9 55

More Fast Tables l l l Returns a const from a table. NO Alignment Issues. Table Start Can Occur ANYWHERE The_CODE movlw 3 call Table_Function movwf temp movlw high Table_start brw movwf PCLATH movlw low Table_start addwf temp, w btfss STATUS, C incf PCLATH, f movwf PCL high Table_start DT 3, 4, 5, 6, 7, 8, 9 56

16 -bit Arithmetic l Carry Support Speeds 16 -bit Math OLD movf addwf movf btfsc addlw addwf NEW lsb_a, w lsb_b, f movf addwf 6 TCY 0 x 01 4 TCY lsb_b, f msb_a, f STATUS, C lsb_a, w movf addwfc msb_a, w msb_b, f 57

Robust Techniques l l RESET instruction Stack Over/Underflow Reset 58

Advanced Topics

Advanced Topics l Accessing the Stack l Accessing the Context Shadows l Reading the Device ID l Preemptive Multitasking l Error Diagnostics 60

Accessing the Stack l Available through the TOS and STKPTR registers l STKPTR is current value of the Stack Pointer l TOS points to the TOP of the STACK l Both registers are read/writeable l TOS is split into TOSH and TOSL, due to the 15 -bit size of the PC 61

Stack Access l The STKPTR indicates current stack position l TOSH, TOSL is the stack at the SPTR position l Changing SPTR will move TOSH, TOSL. l SPTR is 5 bits STKPTR 5 STACK Level. TOSL 0 TOSH Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Level 8 Level 9 Level 10 Level 11 Level 12 Level 13 Level 14 Level 15 TOSH, TOSL 62

Accessing the Context Save Shadow l The interrupt context save registers are read/writeable in bank 31 STATUS_SHAD FSR 0 Low FSR 0 L_SHAD FSR 0 High FSR 0 H_SHAD FSR 1 Low FSR 1 L_SHAD FSR 1 High FSR 1 H_SHAD BSR_SHAD WREG_SHAD PCLATH_SHAD 63

Device ID l Select registers in the Configuration memory are now accessible via the EE interface l The User ID, Device ID and Configuration Word can be read 64

Preemptive Multitasking l Access to the stack and shadows allows an interrupt to replace the current task with a second task l This allows easier RTOS programming for these devices 65

Error Diagnostics l Access to the stack and context shadows also allows more extensive self-check l Stack verification is critical for some safety-critical applications 66

Summary

Summary l Enhanced Core Features: - Program Memory Extended to 32 KB - Data Memory Extended to 2 KB - 14 New Instructions - Simplified Core Register Map - Enhanced Indirect Addressing - Automatic Interrupt Context Saving 68

Thank You!

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