Integrated Development Environment WWW ANDESTECH COM v IDE

Integrated Development Environment WWW. ANDESTECH. COM

v. IDE Page 2 ANDES Confidential

Toolchains And. ESLive Simulator IDE And. ESLive Builder AICE Ande. Shape Ande. Sight Page 3 ANDES Confidential And. ESLive

Ande. Sight IDE v Window v View v Perspective v Editor v Preferences… v Help v Advanced features Page 4 ANDES Confidential

Andes Total SW Solution user Integrated Development Environment (IDE) Ande. Sight™ ICE Simulation Engine Toolchains: Compiler Evaluation Assembler Ande. Shape™ Board And. ESLive™ Linker Debugger So. C Builder Andes SW Solution Page 5 = And. ESLive™ + Ande. Sight™ ANDES Confidential + Ande. Shape™

Integrated Development Environment Toolbar Page 6 ANDES Confidential

Windows v What is window § The overall outer frame v New window § Menu bar Window New Window • Same workspace and perspective § Start another Ande. Sight • Different workspace Page 7 ANDES Confidential

Windows Page 8 ANDES Confidential

Views v What is view § View provides alternative presentations as well as ways to navigate the information in your Workbench. Page 9 ANDES Confidential

Views Page 10 ANDES Confidential

Perspectives v What is perspective § The initial set and layout of views in the Workbench window. § Each perspective provides a set of functionality aimed at accomplishing a specific type of task or works. v We provide § § C/C++ coder Debug VEP Config (Andeslive) Profiling Page 11 ANDES Confidential

Perspectives Page 12 ANDES Confidential

Perspectives – Debug and Profiler Page 13 ANDES Confidential

Perspectives – VEP (Virtual Evalution Platform) Config Page 14 ANDES Confidential

Perspectives – Others… Page 15 ANDES Confidential

Editor v Editors we provide § § § C/C++ Makefile Assembly Binary Hex VEP Page 16 ANDES Confidential

Features of C/C++ Editor v Content assistant v Function Definition v Auto completion v Syntax highlight v Formatter Page 17 ANDES Confidential

Content assistant Page 18 ANDES Confidential

Show Function Definition Page 19 ANDES Confidential

Text Auto Completion Page 20 ANDES Confidential

Template Support Page 21 ANDES Confidential

Formatter Page 22 ANDES Confidential

Preferences v What settings are provided? § Is used to set user preferences § Can be searched using the filter function Page 23 ANDES Confidential

Preferences Page 24 ANDES Confidential

Preference to Change Fonts Page 25 ANDES Confidential

Commands and Functions Page 26 ANDES Confidential

Help System v Context sensitive help § Hot key: F 1 v Help Content v Search … Page 27 ANDES Confidential

Profiling Andesight IDE Trigger Profiling Prof. out Profiling Analysis Engine Profiling data preparation Andeslive Simulator Page 28 ANDES Confidential

Profiling Options v Function Level § § Pure function profiling without branch and cache information With Branch Summary With Cache Summary With Branch and Cache Summary v Branch Level § Pure branch profiling without cache information § With Cache Summary v Views § § Flat View Call View Timeline View Chart View v C and C++ Support v Fast Mode and Extended Mode v Goto Source Page 29 ANDES Confidential

Profiling Options Page 30 ANDES Confidential

Performance Tuning Tune Performance by CPU Configuration Co-Sim Profiling Meet Spec. No Yes END Tune Performance by Software Works Page 31 ANDES Confidential

Tune Performance by Profiler Profile Result of 8 KB I$/D$ Profile Result of 64 KB I$/D$ Page 32 ANDES Confidential

Profiling – Timeline View Page 33 ANDES Confidential

Profiling – Call View Page 34 ANDES Confidential

Profiling – Flat View Page 35 ANDES Confidential

Branch Level with Cache Summary Page 36 ANDES Confidential

Build Options Page 37 ANDES Confidential

Endian – SW SW endian setting gives –EL or –EB option to compiler Page 38 ANDES Confidential

Endian – HW HW endian setting gives option to simulator Page 39 ANDES Confidential

Library – SW SW library setting gives –mlib option to linker Page 40 ANDES Confidential

Library – HW HW library setting should enable Virtual IO support and select proper library for simulator Window > Show View > Other VEP > System Call Emulation Page 41 ANDES Confidential

Toolchain – SW Toolchain includes one for hardcore, one for softcore Page 42 ANDES Confidential

CPU Selection Virtual So. C Builder provides one hardcore and one softcore Page 43 ANDES Confidential

v. Virtual Platform Introduction From physical to virtual and vice versa Page 44 ANDES Confidential

What is Virtual Platform? “It is a system-level simulation model that characterizes real system behavior. It operates at the level of processor instructions, function calls, memory accesses and data packet transfers, as opposed to the bit-accurate, nanosecond-accurate logic transitions of a register transfer level (RTL) model. ”* Andes Development Platform Andes Virtual Platform *from the book ESL Design and Verification: A Prescription for Electronic System Level Design Methodology. B. Bailey, G. Martin and A. Piziali. Elsevier Morgan Kaufmann, 2007 Page 45 ANDES Confidential

S/W Development with Physical H/W Platform Integrated Development Environment SW Developer Desktop Target Hardware Other plug-in tools Applications CM Middleware Operating Systems Profiling Tools BSP/Device Drivers Debugger DEVICE SOFTWARE STACK Build Compiler Source Code Analysis Editor PHYSICAL HARDWARE Physical Target Connection On-Chip-Debug, Ethernet, USB, … Page 46 BSP/Device Drivers ANDES Confidential External System Connectivity

S/W Development with Virtual Platform Integrated Development Environment SW Developer Desktop Other plug-in tools CM Profiling Tools Debugger Applications Build Middleware Compiler Operating Systems Source Code Analysis Editor Tools/API BSP/Device Drivers DEVICE SOFTWARE STACK Virtual Platform External System Connectivity Page 47 ANDES Confidential

v. Andes Virtual Evaluation Platform Page 48 ANDES Confidential

Andeshape™ Platform So. C: AG 101 N 1213 Bus Controller MAC 10/100 USB 2. 0 AHB Bus LCD Controller SDRAM Controller DMA Controller SRAM Controller AHB to APB Bridge PWM I 2 C GPIO INTC WDT Timer RTC APB Bus Power Manager Page 49 ST UART BT UART SSP CF I 2 S ANDES Confidential SD/ MMC

Virtual Evaluation Platform Page 50 ANDES Confidential

S/W Development with Andes Tools Integrated Development Environment SW Developer Desktop (Ande. Sight) Other plug-in tools SOC Builder Ande. Soft Profiler Debugger Applications Program Builder Middleware Compiler Operating Systems Assembler Editor And. ESLive/API BSP/Device Drivers DEVICE SOFTWARE STACK VEP (And. ESLive) Virtual I/O Connectivity Page 51 ANDES Confidential

Ande. ESLive VEP Environment User-defined Models ™ e iv Andes AG 101 L S E d n Peripheral IP Models Andes. Core Model A VEP module Module descriptor SID component Customer So. C Page 52 C/C++ ANDES Confidential

VEP Module slave port ™ e Liv User-defined Models Andes. Core Andes AG 101 S E nd Essential IP Models VEP module A Customer So. C Module descriptor SID component write port master port Page 53 ANDES Confidential read port C/C++ bus port

Andes VEP (a quick summary) v SID, an open-source framework for building simulated Embedded Systems, has been integrated into And. ESLive as backbone simulator v Simulated component, or a SID component, can be written in C/C++, or Tcl to which the SID API is bound v VEP module is a SID component wrapped with XMLbased Module Descriptor in which the parameters and attributes are described v Andes provides sample code (C++-based) and SID example for modeling target (bus slave) and initiator (bus master) components that run on Andeslive v Depending on the requirements from customers, Andes can provide Modeling Training and Services as well Page 54 ANDES Confidential

v. SID Simulator The And. ESLive simulation backbone Page 55 ANDES Confidential

SID Overview v The SID simulator consists of an engine that loads and connects simulated components, based on a simulator configuration file, and runs simulation sessions. v The SID simulator configuration file is a text file that configures a SID simulation run. The configuration file defines the simulation contents, connections, and initial states. v SID comes with a number of simulated components (or SID components), each of which can be modified, configured, or connected to any other independently. v Adding new components is straightforward and does not require any modifications to SID. More info on SID Component Library, refer to the SID Component Developer’s Guide. v While running a simulation, SID can interface with standard I/O, such as a Tk-based visual simulation monitor, the gdb debugger, and the gprofiler. Page 56 ANDES Confidential

SID Architecture (1 of 2) v SID is a simulation framework for supporting embedded systems software development. v SID features a modular architecture of loosely-coupled software components that interact with each other to simulate the behavior of physical hardware parts. v SID components share a fixed low-level API, which defines all possible inter-component communication mechanisms. v SID is packaged as a standalone command-line program that reads and executes a configuration file. v A typical session with SID begins with compiling or assembling code for the simulated system to run, using standard cross-development toolchain, and proceeds through loading the target binary into the simulation environment. Page 57 ANDES Confidential

SID Architecture (2 of 2) v Four Component Types are supported in SID § § Hardware model (hw-xxx) Software model (sw-xxx) Bridge (Tcl/Tk bridge) Special function (event scheduler, host network interface, etc) v Communication mechanisms between Components: § SID API is used to model these mechanisms: • pin, bus, attribute, and relation v The SID API can be thought as the socket on a circuit board. The SID Component is like the IC that plugs into these sockets and the SID simulator configuration file is like the circuit wiring that connects the sockets to each other Page 58 ANDES Confidential

SID Configuration File v The configuration file consists of three major sections: § A listing of component libraries to be loaded (dynamically loaded libraries) • load § A command to instantiate components • new § A set of commands that connect and configure the components • • Page 59 set connect-pin, disconnect-pin (point-to-pint) connect-bus, disconnect-bus (broadcast) relate, unrelate ANDES Confidential

Component Connection in SID CPU (master) Timer (slave) read port out 1 in 1 write port connect-pin CPU out 1 -> Timer in 1 CPU (master) system-mem (accessor) bus slaveport master bus port Memory (slave) data-bus (bus) connect-bus CPU system-mem Memory data-bus Page 60 ANDES Confidential

v. SID Component Modeling Page 61 ANDES Confidential

Basic Component Outline (Class Declaration) #include <sidcomp. h> #include <sidtypes. h> #include <iostream> using sid: : component; using sid: : host_int_4; SID and C++ header files Namespace using class sp_timer : public virtual component { public: sp_timer(); ~sp_timer() throw() {}; protected: input_pin a, b, c; output_pin d, e, f; private: in_out_handler(); } Page 62 Declare this class as SID component and use other predefined utilities Data I/O Inaccessible data and function ANDES Confidential

Component Declaration (1/3) common header files & utility v Header files sidattrutil. h sidbusutil. h sidcomputil. h sidmiscutil. h sidpinattrutil. h sidpinutil. h sidscheutil. h sidtypes. h sidwatchutil. h Page 63 v Tens of utilities v For simplicity issue using namespace sid; using namespace sidutil ANDES Confidential

Component Declaration (2/3) class inheritance class sp_timer : public virtual component //each component class need to inherit from this , public fixed_attribute_map_component //if the component provide configure attribute such as “verbose? ” else use //“no_attribute_map_component” , public fixed_pin_map_component //if the component provide input/output pin else use “no_pin_map_component” , public fixed_bus_component //if the component provide bus access else use “no_bus_map_component” , public no_relation_component //no relation utility requirement , public no_accessor_component //not a bus master Page 64 ANDES Confidential

Component Declaration (3/3) Data I/O //input type input_pin din_pin; friend class callback_pin<sp_timer>; callback_pin<sp_timer> rst_pin; //output type output_pin intr_pin; //clock type (connected to scheduler) friend class scheduler_event_subscription<sp_timer>; scheduler_event_subscription<sp_timer> clk; Page 65 ANDES Confidential

Integrating SID Component in And. ESLive Wrapping SID component with VEP module WWW. ANDESTECH. COM

v. Integrating SID Component in And. ESLive Wrapping SID component with VEP module Page 67 ANDES Confidential

Integrating Component in And. ESLive v To integrate SID component in And. ESLive, slave port an XML-based component descriptor is VEP module created for each component. The component descriptor defines the properties component descriptor to be used in And. ESLive (such as bus, pin, SID write port component read port and attributes) v Once the user-defined component descriptor is completed, save the XML file in the folder: § $ANDESIGHT_ROOT/vep/component/user Page 68 ANDES Confidential master port bus port

Sample Component Descriptor v Component Definition: § § <defcomponent name="hw-sample" shortname="sample" type="SID"> <sid-lib dlsym="sample_component_library" name="libsample. la" /> v Bus Definition: § § <busmaster name="master" type="AHB"/> <busslave name="registers" type="AHB"/> v Pin Definition: § § <defpins name="sample-out-" from="0" to="5" direction="out"/> <defpins name="sample-in-" from="0" to="5" direction="in"/> Page 69 ANDES Confidential

Questions v We want to know how a component is modeled in And. ESLive and what language/description by which the modeling is based upon? v Where can we find the document/tutorial for modeling user-defined components and if Andes can provide modeling training/services? v Will Andes support System. C as a modeling constructor and what if we have System. C models, how can we incorporate them into And. ESLive? Page 70 ANDES Confidential

Answers v We want to know how a component is modeled in The behavior of user-defined model can be written in C/C++ and the SID API is used to compose a SID And. ESLive and what language/description by component by which a VEP-based module is created that runs which the modeling is based upon? on And. ESLive. There is a document in User Manual (release 1. 3. 1) for v Where can we find the document/tutorial for creating a user-defined model. Tutorial is also being modeling user-defined components and if Andes prepared as well as application notes. Andes can provide modeling training/services? modeling training and/or services based on customer requests. In the current release (1. 3. 2), System. C modeling/import is v Will Andes support System. C as a modeling NOT supported in And. ESLive. Andes is now developing SIDinterface and what if we have System. C models, System. C bridge which can communicate System. C interface how can we incorporate them into And. ESLive? with SID-based pin and bus. Untimed System. C models will be supported first. Page 71 ANDES Confidential

v. System. C Modeling v. How VEP can be used in Development Cycle Enable early S/W development Page 72 ANDES Confidential

VEP Use Models v VEP as an Early (or pre-silicon) Software Development and Software Validation Platform § Reduce SW bring-up and system test time § Ideally start SW dev. in parallel to HW dev. § Leave more time for SW dev. and quality assurance v VEP as an Architecture Exploration Platform § Evaluate HW/SW configuration and/or system partitioning § Optimize system architecture v VEP as a RTL Verification Platform § Golden reference models for functional verification § Verify architecture and system validation Page 73 ANDES Confidential

VEP as Early SW Development & Validation v VEP can be used for developing & testing SW (only if the VEP can run as fast as HW board does) § Low-level device drivers and kernel § OS and middleware porting § App. SW development v One scenario is as follows: § SW team extends existing device drivers based on updated IP spec § At the same time, Platform team enhances/creates models (ex. new features added) based on the VEP § SW team completely debugs and tests the driver functionality early on the VEP § SW ‘bring-up’ in a shorter time after the HW (FPGA) is available Page 74 ANDES Confidential

Development Cycle Impact Traditional (or Past) Approach: SW Development (OS & Device Driver Dev, Apps Dev) Platform Specification Hardware Development Final System Testing Integration & Bring-up Debug VEP-based Approach: SW Development Platform Specification Pre-silicon System Test Scalable VEP Hardware Development • Enable Early SW Development Integration Final Bring-up System Debug Testing • Enable Scalable Development • Pre-Silicon System Test • Reduce Bring-up time • Reduce Post-Silicon System Test Scalable Development Page 75 Reducing bring-up and final system test time ANDES Confidential

VEP as Architecture Exploration v VEP can be used to explore design alternatives to determine the appropriate architecture (or system) v Some alternatives to evaluate are: § Andes. Core configuration • Cache, MMU, Local memory, branch prediction, etc § SW profiling (in And. ESLive) • code optimization § HW/SW partitioning • HW accelerator engine or SW oriented • Performance and cost tradeoff § Bus Matrix or Multi-layer • currently NOT supported in And. ESLive Page 76 ANDES Confidential

VEP as RTL Verification v Currently NOT supported in And. ESLive! v Team-up Partnership possibilities § § § GUC (porting Andes. Core ISS with System. C TLM 2. 0) EVE (compiling Andes. Core on Ze. Bu) Co. Ware (porting Andes. Core ISS with System. C/AMBA) Carbon (porting Andes. Core ISS with CASI/System. C) Cadence/Synopsys/Mentor… v Speed is always an important concern and incentive § Transaction-based interface is the key § HW accelerator/emulator may be too expensive to be justified Page 77 ANDES Confidential

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