Chapter 4 UART Serial Port Programming 1 Serial

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Chapter 4 UART Serial Port Programming 1

Chapter 4 UART Serial Port Programming 1

Serial vs. Parallel Data Transfer 2

Serial vs. Parallel Data Transfer 2

Parallel In Serial Out 3

Parallel In Serial Out 3

Serial In Parallel Out 4

Serial In Parallel Out 4

Simplex, Half-, and Full-Duplex Transfers 5

Simplex, Half-, and Full-Duplex Transfers 5

Framing ASCII "A" (0 x 41) 6

Framing ASCII "A" (0 x 41) 6

MAX 232 7

MAX 232 7

MAX 233 8

MAX 233 8

RS 232 Pins Pin 1 2 3 4 5 6 7 8 9 Description

RS 232 Pins Pin 1 2 3 4 5 6 7 8 9 Description Data carrier detect (DCD) Received data (Rx. D) Transmitted data (Tx. D) Data terminal ready (DTR) Signal ground (GND) Data set ready (DSR) Request to send (RTS) Clear to send (CTS) Ring indicator (RI) 9

9 -Pin Male Connector 10

9 -Pin Male Connector 10

DTE-DCE and DTE-DTE Connections 11

DTE-DCE and DTE-DTE Connections 11

Null Modem Connection with Flow Control Signals 12

Null Modem Connection with Flow Control Signals 12

ST-Link-V 2 -1 in Nucleo ST Arm board 13

ST-Link-V 2 -1 in Nucleo ST Arm board 13

ST-Link-V 2 -1 in Nucleo ST Arm board 14

ST-Link-V 2 -1 in Nucleo ST Arm board 14

St-Link/V 2 USART 2 -USB Port Connection 15

St-Link/V 2 USART 2 -USB Port Connection 15

Partial list of USART Registers and their addresses 16

Partial list of USART Registers and their addresses 16

A Simplified Block Diagram of USART 17

A Simplified Block Diagram of USART 17

RCC_CR (RCC Control Register) to showing the HSI Clock Source 18

RCC_CR (RCC Control Register) to showing the HSI Clock Source 18

RCC_CFGR (Clock Configuration Register) Clock Select Resgister bit assignment 19

RCC_CFGR (Clock Configuration Register) Clock Select Resgister bit assignment 19

Clock Generation for USART 2 20

Clock Generation for USART 2 20

APB 1 ENR peripheral clock enable register (RCC_APB 1 ENR) Bit Assignments (Partial Listing)

APB 1 ENR peripheral clock enable register (RCC_APB 1 ENR) Bit Assignments (Partial Listing) 21

BAUD (USART_BRR) Register 22

BAUD (USART_BRR) Register 22

BAUD Rate Register (BRR) Values for Some Baud Rates using OVER=16 and clock of

BAUD Rate Register (BRR) Values for Some Baud Rates using OVER=16 and clock of 16 MHz. 23

BAUD Rate Register (BRR) Values for Some Baud Rates using OVER=8 and clock of

BAUD Rate Register (BRR) Values for Some Baud Rates using OVER=8 and clock of 16 MHz. 24

USART CR 1 (Control 1 Register) bits definition (Partial Listing) 25

USART CR 1 (Control 1 Register) bits definition (Partial Listing) 25

USART Control 2 (USART_CTR 2) register (Partial Listing) 26

USART Control 2 (USART_CTR 2) register (Partial Listing) 26

USART_DR, USART Data Register 27

USART_DR, USART Data Register 27

Status Register (USART_SR) 28

Status Register (USART_SR) 28

GPIO_AFRL (GPIO Alternate Function Register Low) 29

GPIO_AFRL (GPIO Alternate Function Register Low) 29

GPIO_AFRH (GPIO Alternate Function Register High) 30

GPIO_AFRH (GPIO Alternate Function Register High) 30

partial list of STM Arm Pins Used for USART (See Appendix B and Table

partial list of STM Arm Pins Used for USART (See Appendix B and Table 4 -6) 31

GPIOx_MODER (GPIO Mode) for Direction Register (x=A, B, C, . . ) 32

GPIOx_MODER (GPIO Mode) for Direction Register (x=A, B, C, . . ) 32

Alternate Functions (AF) Pin Multiplexing for Port A in STM 32 F 446 Arm.

Alternate Functions (AF) Pin Multiplexing for Port A in STM 32 F 446 Arm. See Appendix B for other Ports. (See AF table for your device) 33