Serial Communication Interface SCI Kevin Stuart Matt Betts

Serial Communication Interface (SCI) Kevin Stuart Matt Betts March 27, 2007 ME 6405, Sp 07

Types of communication l 2 main types l Serial l Telegraph Light Signal Parallel l l ISDN line Factory line

Serial Communication l One line of communication, long string of data Signal Time

Parallel Communication l Many lines of communication, synchronized bursts of data Transmitter Receiver Time

Endianness, how it relates to communication l l l Big Endian- MSB first, less significant bytes in descending order Little Endian- MSB last, data in ascending order Endian type determines how the data is interpreted, and how it should be sent in both serial and parallel communication.

RS 232, SCI, and SPI l l l RS 232 - Typical computer COM port SCI- Serial Communication interface, uses the universal asynchronous receiver/transmitter or UART SPI Serial peripheral interface, part of Port D.

Cable Length / Data Transfer Rate Relation l l As cable lengths increase, signal quality degrades As data transfer speed increases, signal quality degrades much faster for increasing length

Synchronous Communication l l l Clock speed determines the data transfer rate Transmitter and receiver use the same clock to keep signal cohesive. Constantly sending data to maintain clock synchronization, including idle characters.

Asynchronous Communication l l Transmitter and receiver operate independently No synchronization l l So no idle characters HC 11 uses this type of communication

Bit Rate l l l Number of possible on/off switches per second, based on the clock. Faster clock, faster bit rate Standard bit rates Some typical bit rates

Baud Rate l l l Number of actual data bits per second Different from Bit Rate because of required setup bits per word transmitted. Setup bits explained more later

HC 11 SCI registers l 5 major registers l l l BAUD SCCR 1 SCCR 2 SCSR SCDR $102 B $102 C $102 D $102 E $102 F

BAUD Read: Write: l 0 TCLR 0 SCP 1 SCP 0 0 RCKB SCR 2 7 6 5 4 3 2 SCR 1 SCR 0 1 BAUD register, sets speed l l TCLR : Clear baud rate timing chain bit SCP : Baud rate pre-scale select bits RCKB : Baud rate clock test bit SCR : SCI baud rate select bits 0

SCCR 1 Read: R 8 Write: 7 l l l T 8 6 0 5 M 4 Wake 3 0 0 0 2 1 0 SCCR 1 : Serial Communication Interface Control Register 1 R 8 : Receive data bit 8 T 8 : Transmit data bit 8 M : SCI character length bit WAKE : Wakeup method select bit Bits 0 - 2 & 5 are not used (always 0)

SCCR 2 Read: Write: TIE TCIE RIE ILIE TE RE RWU SBK 7 6 5 4 3 2 1 0 SCCR 2 : Serial Communication Control Register 2 TIE : Transmit interrupt enable bit TCIE : Transmit complete interrupt enable bit RIE : Receive interrupt enable bit ILIE : Idle-line interrupt enable bit TE : Transmit enable bit RE : Receive enable bit RWU : Receiver wakeup bit SBK : Send break bit

SCSR Read: TDRE TC RDRF IDLE OR NF FE 4 3 2 1 0 Write: 7 l 6 5 SCI status register l TDRE : Transmit data register empty bit l TC : Transmit complete bit l RDRF : Receive data register full bit l IDLE : Idle-line detect bit l OR : Overrun error bit l NF : Noise flag l FE : Framing Error bit l Bit 0 is not used (always 0) 0

SCDR Read: Write: l R 7 T 7 R 6 T 6 R 5 T 5 R 4 T 4 R 3 T 3 R 2 T 2 R 1 T 1 R 0 T 0 7 6 5 4 3 2 1 0 SCI data register l l l Two separate registers, same address Used to Read the Received data Used to Write the Transmit data R 7 - R 0 – Read bits T 7 - T 0 – Write bits

SPCR Read: Write: l l SPIE SPE DWOM 7 6 5 MSTR 4 CPOL 3 CPHA 2 SPR 1 SPR 0 1 0 Serial Peripheral Interface Control Register SPIE- Serial Peripheral Interrupt Enable l 0 = SPI Interrupts disabled l 1 = SPI Interrupts enabled Serial Peripheral System Enable l 0 = SPI off l 1 = SPI on DWOM – Port D Wired OR mode Option for Port D pins (PD 5: 0) l 0 = Normal CMOS outputs (Leave it as 0) l 1 = Open Drain outputs

How to set up Serial Communication on the HC 11 l l l Set Baud rate using BAUD Set interrupt states using SCCR 2 Set data length using SCCR 1 Make / Set routines to be jumped to when interrupt is triggered Read or Write data to the SCDR Note- Data direction register is overridden by SCI logic

UART (Universal Asynchronous Receiver/Transmitter) l Beforehand Knowledge l Need to know Transmitting speed (and therefore Receiving speed) l Need to know packet construction (# data and formatting bits) l Packet Construction: l Start Bit (1 bit) l Data Bits (8 -9 bits) l l Parity Bit (1 bit) …optional Address Marker (1 bit) …optional Stop Bit (1 bit) Challenge: l Noise

UART: Start Bit l l l 1 Bit (at beginning of message) Only used due to asynchronous nature (synchronous Transmitters/Receivers don’t need start/stop bits) Opposite polarity of data-line’s idle state l Idle state for HC 11 = all 1’s start bit = 0

UART: Data Bits l 8 -9 Bits (in middle of message) l l Most common mode = 8 data bits (SCCR 1, M = 0) Alternative mode = 9 data bits (SCCR 1, M = 1) l l l Can be used for parity Can be used as an address marker (in “address-mark variation”) telling a microprocessor when to sleep or wake up LSB first

UART: Parity Bit (optional) l 1 Bit l l Even Parity l l Parity bit = 1, if # of ones in the set is odd (you make total # even) Odd Parity l l l Located at end of data bits (It is one of the data bits. ) Some say more reliable (guarantees at least one data transition) Parity bit = 1, if # of ones in the set is even (you make total # odd) Note: Parity can be implemented with 8 Data Bits when transmitting ASCII characters (since ASCII is represented with only 7 bits).

UART: Stop Bit l l l 1 bit (at end of message) Only used due to asynchronous nature (synchronous Transmitters/Receivers don’t need start/stop bits) It is the polarity of data-line’s idle state l Idle state for HC 11 = all 1’s stop bit = 1

Ex: Packet Format

Ex: Packet Format-ASCII character ‘H’ (without parity)

Ex: Packet Format-ASCII character ‘H’ (with even parity and odd parity)

Ex: Packet Format-ASCII character ‘l’ (with odd parity)

Ex: Packet Format-ASCII character ‘EOT’ (with odd parity)

UART: Noise l Problem: l l One Solution: l l A premature ‘ 1’ or ‘ 0’ can make the HC 11 Receiver think that it’s receiving data before it really is or that it’s receiving incorrect data. HC 11 takes 3 samples near the middle of each bit time majority decision Another Solution: l Break Command (= all 0’s for >=1 character time, for HC 11) l Used to get attention of Receiver (i. e. change to default rate)

Ex: Full Transmission Format (idle line) EOT ! H e l l o ! EOT = 0 x 48 = 0 b 1001000 = 0 x 65 = 0 b 1100101 = 0 x 6 C = 0 b 1101100 = 0 x 6 F = 0 b 1101111 = 0 x 21 = 0 b 0100001 = 0 x 04 = 0 b 0000100 o l l e H (idle line) l Packet composition = Start Bit + 9 Data Bits [+ Parity Bit (odd parity scheme) as last Data Bit] + Stop Bit l Note: 9 Data Bit transmission was used (instead of 8) so that the receiver doesn’t store the parity bit in the SCDR register. (You can directly store SCDR [the ASCII values] to memory without having to take off the parity bit. )

Advanced Features of HC 11 UART l l HC 11 resynchronizes the Receiver’s bit clock on all 1 -to-0 transitions (instead of just on startup) HC 11 takes 3 logic-samples near the middle of each bit time (majority rules) HC 11’s Receiver can enter a standby mode (“sleep mode”) HC 11 has a TC (Transmit Complete) Flag …in addition to the standard TDRE (Transmit Data Register Empty) Flag.

References: l l M 68 HC 11 ERG/AD Reference Guide (Rev. 2, 10/2003) M 68 HC 11 Reference Manual (Rev. 4, 2001) l l Section 9: p. 317 -366 Wikipedia. org: Asynchronous Serial Communication, UART, Parity l (Used to get a fundamental understanding. )