SERIAL PERIPHERAL INTERFACE SPI M Serial Peripheral Interface

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SERIAL PERIPHERAL INTERFACE (SPI) M Serial Peripheral Interface Module MTT 48 8 -1

SERIAL PERIPHERAL INTERFACE (SPI) M Serial Peripheral Interface Module MTT 48 8 -1

Module Objective Understand SPI format and data transfersgure the control registers Transmit and receive

Module Objective Understand SPI format and data transfersgure the control registers Transmit and receive data Module exercise: Configure the SPI to transmit and receive characters to/from another device in Master mode at a 1 MHz rate M Serial Peripheral Interface Module MTT 48 8 -2

SERIAL PERIPHERAL INTERFACE MODULE Clock Generation Module (CGM) System Integration Module (SIM) LVI IRQ

SERIAL PERIPHERAL INTERFACE MODULE Clock Generation Module (CGM) System Integration Module (SIM) LVI IRQ COP BREAK RESET 68 HC 08 CPU Timer Interface Module (TIM) Direct Memory Access Module (DMA) Internal Bus (IBUS) Serial Communications Interface (SCI) Serial Peripheral Interface (SPI) Random Access Memory (RAM) Electronically Programmable ROM Monitor ROM • Features of the SPI module include the following: • Full-Duplex Operation • Master and Slave Modes • Separate Transmit and Receive Registers • Four Master Mode Frequencies (Maximum = Bus Frequency � 2) • Maximum Slave Mode Frequency = Bus Frequency • Separate Clock Ground for Reduced Radio Frequency (RF) Interference • Serial Clock with Programmable Polarity and Phase • Bus Contention Error Flag • Overrun Error Flag • Two Separately Enabled Interrupts with DMA or CPU Service: SPRF (SPI Receiver Full) SPTE (SPI Transmitter Empty) • Programmable Wired-OR Mode • I 2 C (Inter-Integrated Circuit) Compatibility M Serial Peripheral Interface Module MTT 48 8 -3

SPI I/O Registers Three registers control and monitor SPI operations: • SPI Control Register

SPI I/O Registers Three registers control and monitor SPI operations: • SPI Control Register (SPCR) • SPI Status and Control Register (SPSCR) • SPI Data Register (SPDR) M Serial Peripheral Interface Module MTT 48 8 -4

SPI Modes Master mode • Only a master SPI initiates a transmission • Data

SPI Modes Master mode • Only a master SPI initiates a transmission • Data is shifted out via Master Out Slave In (MOSI) line • Data is shifted in via Master In Slave Out (MISO) line • Transmission ends after 8 cycles of serial clock (SPSCK) Slave Mode • Transfer synchronized to serial clock (SPSCK) from Master • Data is shifted in via the Master Out Slave In (MOSI) line • Data is shifted out via the Master In Slave Out (MISO) line M Serial Peripheral Interface Module MTT 48 8 -5

Slave Select Pin MASTER SLAVE MOSI MISO Shift Register SPSCK Baud Rate Gen. SS

Slave Select Pin MASTER SLAVE MOSI MISO Shift Register SPSCK Baud Rate Gen. SS +5 v SS Slave Select (SS) • Master mode – SS held high during transmission – Acts as error detection input – Can be general purpose output • Slave mode – SS must remain low until transmission completes 0 = Enables slave 1 = Disables slave M Serial Peripheral Interface Module MTT 48 8 -6

SPI Control Register READ: SPCR SPRIE DMAS SPMSTR CPOL CPHA SPWOM 1 0 SPE

SPI Control Register READ: SPCR SPRIE DMAS SPMSTR CPOL CPHA SPWOM 1 0 SPE SPTIE WRITE: RESET: 0 0 0 SPI Control Register (SPCR) • SPI Master (SPMSTR) – Selects master mode or slave mode operation 1 = Master mode 0 = Slave mode • SPI Master and Slave need identical clock polarity and • SPI Enable (SPE) 1 = SPI module enabled 0 = SPI module disabled Recommend disabling SPI before initializing or changing clock phase, clock polarity, or baud rate phase settings • Clock Polarity (CPOL) – Determines clock state when idle • Clock Phase (CPHA) 1 = Begin capturing data on second clock cycle edge 0 = Begin capturing data on first clock cycle edge* – When CPHA = 0, the SS must be deasserted and reasserted between each transmitted byte M Serial Peripheral Interface Module MTT 48 8 -7

Clock Polarity and Phase SPI Control Register (SPCR) • SPI modules need identical Clock

Clock Polarity and Phase SPI Control Register (SPCR) • SPI modules need identical Clock polarity and phase SS CPHA CPOL 0 0 SPSCK 1 0 SPSCK 0 1 SPSCK 1 1 SPSCK MOSI/MISO MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Capture Strobe M Serial Peripheral Interface Module MTT 48 8 -8

SPI Baud Rate READ: SPRF 0 OVRF MODF 0 SPTE SPSCR SPR 1 SPR

SPI Baud Rate READ: SPRF 0 OVRF MODF 0 SPTE SPSCR SPR 1 SPR 0 0 0 WRITE: RESET: 0 0 1 0 SPI Status and Control Register (SPSCR) • SPI rate select bits (SPR 1, SPR 0) – Sets the Master SPSCK clock frequency – No effect in the Slave devices – Baud Rate = CGMOUT / Baud Rate Divisor SPR 1: SPR 0 M System Clock Divided By Baud Rate (System Clock Freq. = 8 MHz) 00 2 01 10 8 4 MHz 1 MHz 32 250 KHz 11 128 62. 5 KHz Serial Peripheral Interface Module MTT 48 8 -9

SPI Data Register READ: Bit 7 SPDR Bit 6 Bit 5 Bit 4 Bit

SPI Data Register READ: Bit 7 SPDR Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WRITE: RESET: UNAFFECTED BY RESET SPI Data Register (SPDR) • Read/Write buffer for SPI data • Write operation – Writes data to transmit data register • Read operation – Reads data in receive data register M Serial Peripheral Interface Module MTT 48 8 -10

SPI Status Flags SPSCR READ: SPRF 0 OVRF MODF SPTE 0 SPR 1 SPR

SPI Status Flags SPSCR READ: SPRF 0 OVRF MODF SPTE 0 SPR 1 SPR 0 0 0 WRITE: RESET: 0 0 1 0 SPI Status and Control Register (SPSCR) • SPI Receiver Full (SPRF) – Set when a byte is shifted from shift register to the receive data register – Cleared by reading SPSCR then reading SPDR 1 = Receive data register full 0 = Receive data register not full • SPI Transmitter Empty (SPTE) – Set when a byte is transferred from SPDR to the shift register – Cleared by reading SPDR register 1 = Transmit data register empty 0 = Transmit data register not empty M Serial Peripheral Interface Module MTT 48 8 -11

SPI Interrupts READ: SPCR SPRIE DMAS SPMSTR CPOL CPHA SPWOM 1 0 SPE SPTIE

SPI Interrupts READ: SPCR SPRIE DMAS SPMSTR CPOL CPHA SPWOM 1 0 SPE SPTIE WRITE: RESET: 0 0 0 SPI Control Register (SPCR) • SPI Receiver Interrupt Enable Bit (SPRIE) – Interrupt generated when SPRF flag set • SPI Transmit Interrupt Enable (SPTIE)) – Interrupt generated when SPTE flag set 1 = Interrupt enabled 0 = Interrupt disabled • Direct Memory Access Select (DMAS) – Selects either DMA or CPU interrupt request – SPRIE/SPTIE bits still enable or disable interrupts M Serial Peripheral Interface Module MTT 48 8 -12

Initialization SPI Initialization sequence 1) Initialize SPI clock frequency ( SPR 1 and SPR

Initialization SPI Initialization sequence 1) Initialize SPI clock frequency ( SPR 1 and SPR 0 in SPSCR ) 2) Set clock configuration ( CPOL and CPHA bits in SPSCR ) 3) Select Master/Slave operation ( SPMSTR in SPCR ) 4) Enable interrupts if desired ( SPTIE, SPRIE in SPCR ) 5) Enable the SPI system ( SPE in SPCR ) • Should enable Master before Slaves M Serial Peripheral Interface Module MTT 48 8 -13

Master to Slave Transfer Simple Polled operation 1) Initialize the SPI 2) Select SS

Master to Slave Transfer Simple Polled operation 1) Initialize the SPI 2) Select SS to Slave device (hardware dependent 3) Write byte to SPDR 4) Wait for SPI Transmitter Empty Flag (SPTE) 5) Read the SPDR 6) Release SS to Slave (hardware dependent) M Serial Peripheral Interface Module MTT 48 8 -14

SPI Exercise Part 1: Initialize a SPI to the following: Master mode 1 MHz

SPI Exercise Part 1: Initialize a SPI to the following: Master mode 1 MHz baud rate ( 8 MHz system clock ) Clock phase = 1 and clock polarity = 0 Polled operation Part 2: Write a procedure to transmit the character in the Accumulator to the Slave device. Then wait for the received character and place it into the Accumulator. (The Master SS is tied to VDD and the Slave SS is tied to ground) M Serial Peripheral Interface Module MTT 48 8 -15

M Serial Peripheral Interface Module MTT 48 8 -16

M Serial Peripheral Interface Module MTT 48 8 -16

Additional Information Wired-Or Mode READ: SPCR SPRIE DMAS SPMSTR CPOL CPHA SPWOM 1 0

Additional Information Wired-Or Mode READ: SPCR SPRIE DMAS SPMSTR CPOL CPHA SPWOM 1 0 SPE SPTIE WRITE: RESET: 0 0 0 SPI Control Register (SPCR) • SPI Wired OR Mode (SPWOM) – Configures MISO, MOSI, and SPSCK outputs to be open-drain drivers – Allows multiple-master systems – Provides some protection against CMOS latchup M Serial Peripheral Interface Module MTT 48 8 -17

Additional Information Overflow and Mode Fault Status Flags SPSCR READ: SPRF 0 OVRF MODF

Additional Information Overflow and Mode Fault Status Flags SPSCR READ: SPRF 0 OVRF MODF 0 SPTE SPR 1 SPR 0 0 0 WRITE: RESET: 0 0 1 0 SPI Status and Control Register (SPSCR) • Overflow flag (OVRF) – Failure to read data register before it is over written – Incoming data bytes are lost • Data register contents unaffected – Cleared by reading the data register • Mode Fault flag (MODF) – Master mode only – Indicates another master tried to access this device – Set when another device pulls SS pin low – Cleared by a write to the SPSCR M Serial Peripheral Interface Module MTT 48 8 -18

Additional Information Low Power Modes • WAIT – SPI mode remains active – SPI

Additional Information Low Power Modes • WAIT – SPI mode remains active – SPI registers are not accessible • Except by DMA – Enabled SPI interrupts will exit wait mode • STOP – SPI module becomes inactive – No affect on register conditions – Operation continues after an external interrupt M Serial Peripheral Interface Module MTT 48 8 -19

Register Summary READ: SPCR SPRIE DMAS SPMSTR CPOL CPHA SPWOM SPE SPTIE WRITE: SPSCR

Register Summary READ: SPCR SPRIE DMAS SPMSTR CPOL CPHA SPWOM SPE SPTIE WRITE: SPSCR READ: SPRF 0 OVRF MODF SPTE 0 SPR 1 WRITE: SPR 0 READ: Bit 7 SPDR Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WRITE: M Serial Peripheral Interface Module MTT 48 8 -20

M Serial Peripheral Interface Module MTT 48 8 -21

M Serial Peripheral Interface Module MTT 48 8 -21