The World Leader in HighPerformance Signal Processing Solutions

The World Leader in High-Performance Signal Processing Solutions Data Conversion Fundamentals Analog-Digital Converters

The World Leader in High-Performance Signal Processing Solutions Introduction to A/D Converters

A/D Converter (ADC) Introduction u A/D l l Fundamentals Sampling Quantization u Factors l l Static Performance Dynamic Performance u ADC l l Affecting A/D Converter Performance Architectures SAR ADCs Pipelined ADCs Flash Type ADC Sigma-Delta ADCs u High Speed ADC Application Considerations

The Measurement & Control Loop ANALOG SIGNAL PROCESSOR MUX • Operational Amp • Differential Amp • Instrumentation Amp • Isolation Amp MUX A-D CONVERTER • Multiplier/Divider • Log Amplifier • rms-dc Converter • F-V/V-F Converter REFERENCE ANALOG SIGNAL PROCESSOR D-A CONVERTER n bits MICRO PROCESSOR OR DSP PROCESSOR n bits

“REAL WORLD” SAMPLED DATA SYSTEMS CONSIST OF ADCs and DACs ADC SAMPLED AND QUANTIZED WAVEFORM DAC RECONSTRUCTED WAVEFORM

What is an Analog-Digital Converter? REFERENCE INPUT ANALOG INPUT RESOLUTION N BITS DIGITAL OUTPUT Analog Input DIGITAL OUTPUT CODE = x (2 N - 1) Reference Input Produces a Digital Output Corresponding to the Value of the Signal Applied to Its Input Relative to a Reference Voltage u Finite Number of Discrete Values : 2 N Resulting in Quantization Uncertainty u Changes Continuous Time Signal into Discrete Time Sampled Representation u Sampling and Quantization Impose Fundamental yet Predictable Limitations u

Sampling Process u Representing a continuous time domain signal at discrete and uniform time intervals u Determines maximum bandwidth of sampled (ADC) or reconstructed (DAC) signal (Nyquist Criteria) u Frequency Domain- “Aliasing” for an ADC and “Images” for a DAC

Quantization Process u Quantization l l l Process Representing an analog signal having infinite resolution with a digital word having finite resolution Determines Maximum Achievable Dynamic Range Results in Quantization Error/Noise Any Analog Input in this Range Gives the Same Digital Output Code

Conversion Relationship for an Ideal A/D Converter DIGITAL OUTPUT 111 110 101 100 1 LSB 011 010 001 1/8 2/8 3/8 4/8 5/8 6/8 ANALOG INPUT 7/8

DIGITAL OUTPUT Quantization Noise 111 110 101 100 011 010 001 1/8 2/8 3/8 4/8 5/8 6/8 7/8 NORMALIZED ANALOG INPUT FS q = 1 LSB quantization noise error

Quantization Noise (con’t) +q/2 0 volts -q/2 u The RMS value of the quantization noise sawtooth is its peak value, q¸ 2, divided by Ö 3, or q ¸ Ö 12 u For Sine Wave Full Scale RMS Value is 2 (N-1)/Ö 2 u For Saw Tooth Quantization Error Signal RMS Value is q /Ö 12 u Thus S/N is 1. 225 x 2 N u Expressed in d. B as 1. 76 + 6. 02 N, where N is the resolution of the A/D converter

Quantization Noise (con’t) HARMONICS OF FSIGNAL (EXAGGERATED FOR CLARITY) OUTPUT RMS QUANTIZATION NOISE FSIGNAL u If FS/2 FS the quantization noise is uncorrelated with the frequency of the AC input signal, the noise will be spread evenly over the Nyquist bandwidth of Fs/2. u If, however the input signal is locked to a sub-multiple of the sampling frequency, the quantization noise will no longer appear uniform, but as harmonics of the fundamental frequency

ADC Resolution vs. Quantization Parameters

Analog Input Signal Definitions

Unipolar and Bipolar Converter Codes FS - 1 LSB 0 0 ALL "1"s 1 AND ALL "0"S -FS UNIPOLAR OFFSET BINARY ALL "1"s -(FS - 1 LSB) 2’s COMPLEMENT

Factors Affecting A/D Converter Performance - Offset And Gain for Unipolar Ranges ACTUAL IDEAL GAIN ERROR IDEAL ZERO ERROR OFFSET NO GAIN ERROR: ZERO ERROR = OFFSET ERROR 0 WITH GAIN ERROR: OFFSET ERROR = 0 0

Factors Affecting A/D Converter Performance - Offset And Gain for Bipolar Ranges ACTUAL IDEAL 0 0 ZERO ERROR OFFSET ERROR NO GAIN ERROR: ZERO ERROR = OFFSET ERROR ZERO ERROR WITH GAIN ERROR: OFFSET ERROR = 0 ZERO ERROR RESULTS FROM GAIN ERROR

DC Specifications (Ideal) u Ideal ADC code transitions are exactly 1 LSB apart. u For an N-bit ADC, there are 2 N codes. (1 LSB = FS/ 2 N ) u For this 3 -bit ADC, 1 LSB = (1 V/23 = 1/8 th) u Each “step” is centered on an eighth of full scale

DC Specifications (DNL) u Differential Non-Linearity (DNL) is the deviation of an actual code width from the ideal 1 LSB code width u Results in narrow or wider code widths than ideal and can result in missing codes u Results in additive noise/spurs beyond the effects of quantization

DC Specifications (DNL) u DNL error is measured in lsbs. u A given ADC will have a typical DNL pattern. u These patterns will also have an element of randomness to them.

DC Specifications (INL) u Integral Non-Linearity (INL) is the deviation of an actual code transition point from its ideal position on a straight line drawn between the end points of the transfer function. u INL is calculated after offset and gain errors are removed u Results in additive harmonics and spurs

DC Specifications (INL) u Some typical INL patterns Bow indicates 2 nd order nonlinearity “S” indicates 3 rd order nonlinearity

QUANTIFYING ADC DYNAMIC (AC) PERFORMANCE u Harmonic Distortion u Worst Harmonic u Total Harmonic Distortion (THD) u Total Harmonic Distortion Plus Noise (THD + N) u Signal-to-Noise-and-Distortion Ratio (SINAD, or S/N +D) u Effective Number of Bits (ENOB) u Signal-to-Noise Ratio (SNR) u Analog Bandwidth (Full-Power, Small-Signal) u Spurious Free Dynamic Range (SFDR) u Two-Tone Intermodulation Distortion u Noise Power Ratio (NPR) or Multitone Power Ratio (MPR)

Dynamic Testing of A/D Converters POWER LOW PHASE SUPPLIES JITTER SAMPLING CLOCK SOURCE LOW PHASE JITTER SINEWAVE SOURCE u BANDPASS FILTER A/D CONVERTER ON EVALUATION BOARD FFT ANALYZER A Fast Fourier Transform (FFT) Analyzer is used to measure dynamic performance

amplitude Fast Fourier Transform converts f 1 2 f 1 this… 3 f 1 . . . to this amplitude time f 1 2 f 1 3 f 1 frequency

An M-Point FFT 0 d. B SNR = 6. 02 N + 1. 76 d. B RMS Quantization Noise Level FFT Floor = 10 log 10 (M ¸ 2) 18 d. B, M = 128 21 d. B, M = 256 24 d. B, M = 512 27 d. B, M = 1024 30 d. B, M = 2048 33 d. B, M = 4096 Bin Spacing = D F = FS ¸ M The Effective Noise Floor of an M-Point FFT Is Less Than The RMS Value of the Quantization Noise

Actual FFT Plot for AD 7484, 14 -Bit SAR ADC Sampling at 3 MHz

Nyquist Bandwidth & Aliasing u 2 Signals that are Mixed Together Produce Sum and Difference Frequency Components u Nyquist Theory Stipulates that the Signal Frequency, FSIGNAL must be < to ½ FSAMPLING to Prevent a Condition Known As “Aliasing”, in which the Difference Component Appears Within the Signal Bandwidth of Interest

The Nyquist Bandwidth & Aliasing (FSIGNAL < ½ FSAMPLING) fsignal fsampling - fsignal fsampling + fsignal passband 1 MHz 3 MHz 4 MHz 5 MHz The Signal Frequency Is < 1/2 the Sampling Frequency and So the Sum and Difference Components Fall Outside (Beyond) the Signal Passband

The Nyquist Bandwidth & Aliasing (FSIGNAL > ½ FSAMPLING) fsampling- fsignal “Alias” 0. 5 MHz fsignal 1 MHz fsampling 1. 5 MHz fsampling + fsignal 2. 5 MHz The Signal Frequency Is > 1/2 (approx 2/3) the Sampling Frequency. An “Alias” or False Image is Thus Created that Falls Within the Passband of Interest.

SINAD, ENOB, and SNR u SINAD l (Signal-to-Noise-and-Distortion Ratio) The ratio of the rms signal amplitude to the mean value of the root-sum-squares (RSS) of all other spectral components, including harmonics, but excluding dc u ENOB (Effective Number of Bits) l u SNR (Signal-to-Noise Ratio, or Signal-to-Noise Ratio Without Harmonics) l The ratio of the rms signal amplitude to the mean value of the root-sum-squares (RSS) of all other spectral components, excluding the first five harmonics and dc

ADC LARGE SIGNAL (OR FULL POWER) BANDWIDTH u Full-power bandwidth is defined as the input frequency where the fundamental in an FFT of the output, rolls off to its 3 d. B point u ADC’s SHA generally determines the FPBW l l FPBW often limited by slew rate of the internal circuitry. May not be compatible with the converter’s maximum operating rate u u l Ideally f. FPBW >> fs / 2 Many High Speed Converters have f. FPBW < fs / 2 Use as a “prerequisite” specification for comparing ADC’s IF undersampling capabilities. But need to consider distortion as well.

Successive Approximation ADC “Recursive” One-Bit Sub-Ranging Architecture

Successive Approximation ADC

How a Successive Approximation A/D Converter Works u Rising/Falling Edge of Convert Start Pulse Resets Logic u Falling/Rising Edge Begins Conversion Process u Bit Comparisons Made on Each Clock Edge u Conversion Time Equals Number of Comparisons (Resolution) Times Clock Period u The Accuracy of Conversion Depends on the DAC Linearity and Comparator Noise

How Successive Approximation Works EXAMPLE : ANALOG INPUT = 6. 428 V, REFERENCE = 10. 000 V MSB 5. 000 V 2 SB 2. 500 V 3 SB 1. 250 V LSB 0. 625 V VIN > 5. 000 V VIN > 7. 500 V VIN > 6. 250 V VIN > 6. 875 V YES NO 1 0

Successive Approximation ADC Advantages to SAR A/D converters • Low Power (12 -bit/1. 5 MSPS ADC: 1. 7 m. W) • Higher • Small • No resolutions (16 -bit/1 MSPS) Die Area and Low Cost pipeline delay Tradeoffs to SAR A/D converters • Lower sampling rates Typical Applications • Instrumentation • Industrial • Data control acquisition

Pipelined Sub-ranging ADC Conversion divided into discrete stages thus causing pipeline delay l 1 st Stage ADC is 6 -bit FLASH l 2 nd Stage ADC is 7 -bit Flash l Total resolution is 12 bits (one bit used for error correction)

Pipelined Sub-ranging ADC

Pipelined Sub-ranging ADC Advantages to Pipelined Sub-ranging A/D converters • Higher resolutions at high-speeds (14 -bits/105 MSPS) • Digitize • Tradeoffs converters wideband inputs to pipelined sub-ranging A/D • Higher power dissipation • Larger die size Typical Applications • Communications • Medical • Radar imaging

Flash or Parallel ADC 2 N-1 comparators form the digitizer array, where N is the ADC resolution Analog input is applied to one side of the comparator array, a 1 lsb reference ladder voltage is applied to the other inputs. The comparator array is clocked simultaneously and decides in parallel. Output logic converts from thermometer code to binary

Flash or Parallel ADC Advantages to Flash A/D converters • Fastest • Low conversion times (up to 1 GSPS) data latency Tradeoffs to Flash A/D converters • Higher • High power consumption capacitive input is difficult to drive Typical Applications • Video digitization • High-speed data acquisition

FIRST-ORDER SIGMA-DELTA ADC CLOCK Kfs INTEGRATOR VIN + ò å fs A + _ _ DIGITAL FILTER AND DECIMATOR LATCHED COMPARATOR (1 -BIT ADC) B +VREF 1 -BIT DAC 1 -BIT DATA STREAM –VREF SIGMA-DELTA MODULATOR 1 -BIT, K fs N-BITS fs

OVERSAMPLING, DIGITAL FILTERING, NOISE SHAPING, AND DECIMATION A fs QUANTIZATION NOISE = q / 12 q = 1 LSB Nyquist Operation ADC B Oversampling + Digital Filter Kfs + Decimation ADC C Kfs SD MOD fs fs 2 DIGITAL FILTER DIGITAL DEC FILTER Oversampling + Noise Shaping + Digital Filter + Decimation fs REMOVED NOISE fs 2 Kfs 2 fs DIGITAL DEC FILTER Kfs REMOVED NOISE fs 2 Kfs

DEFINITION OF "NOISE-FREE" CODE RESOLUTION = log 2 FULLSCALE RANGE RMS NOISE BITS NOISE-FREE = CODE RESOLUTION log 2 FULLSCALE RANGE P-P NOISE BITS EFFECTIVE RESOLUTION P-P NOISE = NOISE-FREE = CODE RESOLUTION 16. 5 bits 6. 6 × RMS NOISE log 2 20 m. V FULLSCALE RANGE 6. 6 × RMS NOISE BITS 0. 4 u. Vrms = EFFECTIVE RESOLUTION – 2. 72 BITS

SIGMA-DELTA ADCs Advantages to Sigma-Delta A/D converters • High resolutions and accuracy (24 -bits) • Excellent • Noise DNL and INL performance shaping capability Tradeoffs in Sigma-Delta A/D converters • Limited input bandwidth • Slower sampling rates Typical Applications • Precision • Medical data acquisition and measurement instrumentation

High Speed ADC Time Domain Specifications Considerations u Aperture Jitter and Delay u ADC Pipeline Delay u Duty Cycle Sensitivity u DNL Effects

EFFECTS OF APERTURE AND SAMPLING CLOCK JITTER u Jitter: l Most systems assume the signal is sampled uniformly Clock noise leads to non-uniform sampling (i. e. jitter) l Jitter leads to SNR degradation for high frequency inputs: l

SNR DUE TO APERTURE AND SAMPLING CLOCK JITTER

EFFECTIVE APERTURE DELAY TIME u Typically not an issue in frequency domain applications u May vary slightly among devices of same product due to variations in SHA bandwidth and CLK prop. delays

ADC LATENCY OR PIPELINE DELAY u Many High Speed ADC’s, such as subranging types, use pipeline architectures to: l l l Reduce chip size, and power consumption Allows multiple samples to be converted simultaneously in ADC Results in fixed delay between Sampled Input and corresponding digital output.

ADC DUTY CYCLE SENSITIVITY u High Speed ADCs are often sensitive to duty cycle of the CLK input l l CLK oscillators are usually specified as 40/60 or 45/55 Digital Specifications of datasheet provide a minimum CLK HIGH/LOW period (nsec) to achieve rated performance. Some datasheets show SNR/THD graphs as a function of duty cycle Note, ADC also has minimum specified sample rate

DNL ERRORS LIMIT IDEAL NOISE AND SPUR FLOOR PERFORMANCE u Ideal ADC code transitions are exactly 1 LSB apart. DNL is the deviation from this value. u Results in additive noise/spurs beyond the effects of quantization u Limits ultimate achievable SNR and low level signal SFDR performance u l Predictable for a given device once error transfer function is known. l DNL error pattern varies among devices of a given product Dynamic correction techniques include adding “dither” or element shuffling

Example : AD 9433 SFDR DISABLED ENABLED

Example : AD 9433 SFDR ENABLED DISABLED Encode = 105 Msps Ain = 70 MHz, -0. 5 d. BFs

Example of Data Sheet Specifications for AD 9430 ADC

Example of Data Sheet Specifications for AD 7476 ADC

For complete information on the World’s most extensive line of A/D converters visit WWW. ANALOG. COM