The World Leader in High Performance Signal Processing

The World Leader in High Performance Signal Processing Solutions Audio ADC/DACs Primer David Hossack

Goals u Learn about a real world signal processing application There are hundreds of these in this room…. . l Also on DSP Board l u Learn l about commercial considerations Ask u Agenda Start at actual A/D conversion l Motivate sigma-delta modulator l Motivate interpolation and decimation filters l Example filters l u No equations – simple overview u Ask 2 questions

Audio Codec on DSK physically large package by today’s standards 3

Analog/Digital Signal Conversion u Converting two things: l Continuous Time <-> Discrete Time u Sampling l l l Need clock for discrete time u Concern on clock jitter at interface between discrete-to-continuous Continuous Value <-> Discrete Value u Quantization l u Eg Switched capacitor DAC u Digital (discrete time, discrete value) u -> analog, discrete time l u 4 Number of levels or number of bits – eg 16 bit or 24 bit These conversions can happen separately l u Sample rate – samples/s or “Hz” – eg 44. 1 k. Hz or 48 k. Hz Continuous time, but still sampled -> analog, continuous time Not necessarily a one-to-one transformation between input samples and output samples

Typical Specs for Audio Converters u SNR – measure of additive noise 90 -120 d. B l “A-weighted” l Bandwidth u 20 -20 k. Hz l u THD l – measure of errors at harmonics of input – nonlinearity 80 -110 d. B u These are “AC” Specs u “Traditional” converter specs not appropriate Absolute accuracy l Integral non-linearity l Differential non-linearity l Conversion Time l 5

What does 100 d. B mean? u “CD quality” l l u Absolute accuracy is not important Linearity fairly important Noise very important Hard to design audio converter using only component matching l l 6 1% easy, >12 bits usually requires calibration or signal processing Need to be careful to determine how errors manifest For audio: l l l u 1 part in 100000 Component matching on silicon l l u u N= 16 bits => approx 6 N + 2 => 98 d. B u With assumptions regarding the signal and error pdfs u Flat weighting, full bandwidth Sigma-Delta Modulation is a signal processing method to solve this Introduces its own problems u Oversampling u Out of Band Noise u Non-linear system that is hard to fully analyze 0. 001% with care : 0. 1% Errors Specs: • Offset • Gain • Linearity • Noise

Sigma Delta Modulation u Method for obtaining high resolution signal conversion without requiring high component matching Quantizes input to small number of levels l Signal detail is preserved and obtaining by filtering l u Requires signal processing u Requires oversampling, requires sample rate conversion filters ADC – decimation (downsampling with filtering) l DAC – interpolation (upsampling with filtering) l u Economics l Moore’s law allowed the DSP implementation to be cost effective u In l 7 limited adoption until approx 1990 engineering, the “rules” and constraints are always changing Implementations have changed significantly over the years

Almost all audio converters use Sigma Delta Modulation u Delta Sigma ≡ Sigma-Delta u Other applications of Sigma-Delta l Communications u Cell Phones Modulator Based Converters: u Quantizer l Memoryless Non-Linear Function u Loop l l Filter Quantization decisions affect future quantization decisions Has effect of making the quantizer behave more linearly u Oversampling l l 128 x typical 48 k. Hz x 128 => 6. 144 MHz u Sigma. Delta l l 8 Modulator Loop Filter Coarse quantizer Quantization error are made to appear at high frequencies Desired signal is at low frequencies

One bit vs Multi-bit In the one-bit D/A converter, clock jitter in the over sampling clock translates directly into D/A errors - causing gross errors, increasing noise and reducing the sound quality. In a multibit sigma-delta made up of multiple two-level D/A converters, the D/A output looks more like an analog signal, making it less sensitive to jitter and easier to filter. 9

Linear Signal Processing Model of SDM u Replace l What u Noise quantiser by a linear gain value for two level quantizer Transfer Function (NTF) l The shape of the quantization noise l Most of the energy is at high frequencies u Signal Transfer Function (STF) l The transfer function from the input to the putput l Can be flat (delay or no delay) u See 10 books, Matlab SDM Toolbox

Sigma-Delta DAC u Two Level DAC l No matching problems l Errors are gain, offset l Horrible out of band noise l Non-linearities due to inter symbol interference and slew rate limiting u Multilevel DAC u Implementations l Switched Capacitor u Continuous amplitude, discrete time filter l Current Source 11

Multi Level DAC 12

SDM DAC Stages u Digital Interpolation 2 x Interpolator u Upsample by 2 u Halfband (FIR) u Allpass based structure (IIR) l CIC Interpolator u Often Linear Interpolator Sinc 2 l Also need CIC compensation filter l u Digital l Sigma Delta Modulator Dynamic Element Matching 2 x → 4 x 4 x → 128 x Also designed using sigma-delta techniques 128 x u Analog 13 1 x → 2 x DAC → 17 levels → 16 of 2 level

SDM ADC Stages u Analog l 2 -17 Sigma Delta Modulator Levels (1 -16 decision thresholds) u Digital Decimation 128 x l CIC Down Sample by 32 u Sinc 4 l 2 x Decimator u Down Sample by 2 u Halfband (FIR) l Allpass based structure (IIR) l 128 x → 4 x 4 x → 2 x l 2 x Decimator u Down Sample by 2 Halfband (FIR) l Allpass based structure (IIR) l l Also 14 need CIC compensation filter 2 x → 1 x

CIC Filter u Recursive Filter Structure – yet FIR Pole / Zero Cancellation l Need to use modulo arithmetic l u Efficient for Interpolation and Decimation u Very good transfer function for large rate changes Interpolator – images of signals near dc are suppressed l Decimator – frequencies that will alias to near DC suppressed l u Very 15 simplementation Graphic from wikipedia

Many diagrams taken from this paper: 16

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Component Responses – Continuous Coefficients Sinc 2 FIR 1 20

Digital Filter Implementation u Use l CIC filters at higher sample rates Cost efficient structure for implementing restricted set of FIR filters u Use FIR/IIR Filters at lower sample rates Exploit structural symmetries u Eg Half band FIR interpolator uses input samples directly l Eg Half-band or parallel all-pass filters u Restricted responses l Compensation required for CIC filters l u CIC often implemented flat u FIR/IIR usually implemented l l l Fixed program – hardwired in logic Single multiplier or multiplier equivalent Eg Canonic Signed Digit / Signed Power of Two “multiplierless” Multiple channels implemented by single DSP engine u Cost/Power l 21 by a simple DSP engine important – not on digital process Eg 0. 35 u or 0. 18 u rather than say 65 nm or 45 nm for analog reasons

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Signal Processing Design and Optimization u Oversampling Rate for Analog Converter u Number of levels for Analog Converter u Filter architecture l Number of Stages l Type (CIC/FIR/IIR) of stage u Limit Memory Requirement u Limit Coefficient Wordlength or number of CSD/SPT terms l Affects filter response l <16 bit typical u Limit Data Wordlength requirement l Affects SNR, quantization effects l 20 -24 bit typical u No 25 floating point!

Signed Power of Two Coefficients u Digitally “easy” coefficients l 0 l +1, -1 l +1/2, -1/2 l +1/4, -1/4 l… u Sums of these l Eg l +1/2 – 1/16 + 1/128 u Compare l Only with Booth encoding used in multipliers need a fixed set of coefficients l Less general – opportunity to optimize 26

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A very simple DSP 24 bit Two’s complement One FIR tap calculated per clock cycle - Already have higher clock rate available 24 bit Two’s complement or SPT 28

Component Responses – Continuous Coefficients Sinc 2 FIR 1 29

Full Response with Continuous Coefficients 30

Full Response with SPT Coefficients 31

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Gentler Frequency Response Requires higher sampling rate 33

Summary u Audio ADC and DAC is a rich example of real world signal processing u System l Use u Filter l CIC u Filter / Architectural Level Design digital technology to overcome weaknesses in analog Architectural Design vs FIR vs IIR Optimization l Structure l Word 34 lengths of coefficients and data

Presented By: David Hossack Analog Devices, Inc. 804 Woburn Street Wilmington MA 01887 david. hossack@analog. com 35