Methodology for Electromigration Signoff in the Presence of

Methodology for Electromigration Signoff in the Presence of Adaptive Voltage Scaling Wei-Ting Jonas Chan, Andrew B. Kahng and Siddhartha Nath VLSI CAD LABORATORY, UC San Diego / VLSI CAD Laboratory -1 -

Outline n n Motivation Previous Work n Analysis Models Experimental Setup and Results n Conclusions n -2 -

Bias Temperature Instability (BTI) |ΔVth| increases when device is on (stressed) |ΔVth| is partially recovered when device is off (relaxed) |Vgs| ON OFF time Device aging (|ΔVth|) accumulates over time NBTI: PMOS PBTI: NMOS [Vattikonda. WC 06] -3 -

Electromigration in Interconnects n Electromigration (EM) is the gradual displacement of metal atoms in an interconnect n Iavg causes DC EM and affects power delivery networks n Irms causes AC EM and affects clock and logic signals -4 -

Adaptive Voltage Scaling (AVS) n n Accumulated BTI higher |ΔVth| slower circuit AVS can compensate for performance degradation Circuit performance Circuit On-chip aging monitor Without AVS With AVS target time Voltage regulator Closed-loop AVS Circuit performance Vdd time -5 -

BTI + AVS Signoff n n Ensure circuit meets timing requirements under BTI aging Use AVS to offset BTI degradation Step 1 VBTI | Vt| Vlib ? Vfinal Step 2 Step 3 Derated library Circuit implementation and signoff BTI degradation and AVS netlist Signoff loop of BTI -6 -

EM + BTI + AVS Signoff? n n Aggressive AVS scheduling results in more severe degradation Guardband during implementation increases due to degradation Stress on Wires Vfinal Vlib , VBTI Design Implementation Derated Libraries EM loop BTI loop Signoff loop of BTI + EM n How to signoff for EM with AVS? What area, power costs? n What is the impact to EM lifetime? n -7 -

Outline n n Motivation Previous Work n Analysis Models Experimental Setup and Results n Conclusions n -8 -

Previous Works n EM lifetime and wire degradation models – Closed-form lifetime models (Black, Arnaud et al. , Federspiel et al. ) – Statistical model for wire degradation (Mishra et al. ) n n Claim their model reduces pessimism in Black’s Equation EM-durable circuits – Wire-sizing algorithms (Adler et al. , Jiang et al. ) – Wire segmentation and via insertion algorithms (Li et al. ) – Current-aware routers (Lienig et al. , Yan et al. ) n BTI Signoff – Interactions between AVS and BTI (Chan et al. , Chen et al. , Basoglu et al. ) No studies on three-way interactions between BTI, EM and AVS!!! -9 -

Outline n n Motivation Previous Work n Analysis Models Experimental Setup and Results n Conclusions n -10 -

EM Model: Black’s Equation n n EM degrades interconnect lifetime Black’s Equation calculates lifetime of interconnect segment due to EM degradation n n n n t 50 – median time to failure (= loge 2 x MTTF) A* – geometry-dependent constant J – current density in interconnect segment n – constant ( = 2) Ea – activation energy of metal atoms k – Boltzmann’s constant T – temperature of the interconnect -11 -

New EM Model: Mishra-Sapatnekar Models resistance increase due to voids in wires instead of MTTF Derived from statistical model of nucleation and growth time n n Log-normal distribution -12 -

New EM Model: Impact on Signal Wires n n n Sweep different gate sizes up to 8× Larger gates do not necessarily help to reduce EM impact ∼ 8% delay degradation for buffers smaller than 4× when resistance increases to high values (∼ 146%) 1 X 2 X 3 X 4 X 6 X 2. 0 E-09 1. 5 E-09 1. 0 E-09 5. 0 E-10 0. 0 E+00 100% 110% 121% 133% 146% 161% 177% 195% 214% 236% 259% 285% 314% 345% 380% 418% 459% 505% 556% Delay (sec) 2. 5 E-09 Statistical model is optimistic in predicting delay penalties (∆R+R 0)/R 0 -13 -

New EM Model: Impact on Signal Wires n n Sweep FO 4 capacitive load by factors {1. 0×, 1. 6×, 2. 1×} EM slows down circuit performance due to Ø increased stage delay Ø increased output transition times 3. 0 E-09 1 1. 6 2. 1 Gate = 8 X 2. 0 E-09 1. 0 E-09 0. 0 E+00 100% 110% 121% 133% 146% 161% 177% 195% 214% 236% 259% 285% 314% 345% 380% 418% 459% 505% 556% Delay (sec) 4. 0 E-09 Multiple of FO 4 Delay increases by ~35% with large resistance increase ~200% (∆R+R 0)/R 0 -14 -

Outline n n Motivation Previous Work n Analysis Models Experimental Setup and Results n Conclusions n -15 -

Experimental Setup n n n Multiple implementations based on different signoff corners AES and DMA designs from Opencores 28 nm foundry FDSOI technology Commercial tool-based SP&R flows Synopsys Prime. Time for timing analysis Matlab for AVS simlulation with BTI and EM -16 -

AVS Signoff Corner Selection Impl# 1 2 3 4 5 6 7 8 Vlib(V) Vmin Vmax Vmin 0. 98 V 0. 97 V 0. 96 V 0. 95 V VBTI (V) Vmin Vmax N/A 0. 98 V 0. 97 V 0. 96 V 0. 95 V • Characterize different derated libraries against BTI • Evaluate impact of library characterization • Vfinal is predicted by cell chains ahead of implementation • Eight implementations 1 : VBTI = Vlib = Vmin Ignore AVS 2 : Most pessimistic derated library 3 : VBTI = Vlib = Vmax Extreme corner for AVS 4 : No derated library (reference) 5 : Sweep around Vfinal 6 : Vfinal by cell chain prediction [Chan. CK 13] 7 : Sweep around Vfinal 8 : Sweep around Vfinal -17 -

AVS Signoff Corner Selection Non-EM Aware After Fixing (Black's) Power (m. W) 32 30 28 26 24 22 20 10000 After Fixing (Mishra) AES 2 Optimistic about AVS Pessimistic about AVS 3 3 3 6 6 77 78 6 4 8 55 48 1 5 4 1 1 12000 14000 2 2 16000 18000 20000 22000 Area (μm 2) -18 -

AVS Impact on EM Lifetime • Assume no EM fix at signoff • BTI degradation is checked at each step and MTTF is updated as Lifetime (year) 12 Vfinal (V) 1. 2 30% MTTF penalty 10 1. 1 8 6 1 4 2 0 0. 9 200 m. V voltage compensation 1 2 3 4 5 6 Implementation # 7 8 Vfinal (V) Lifetime (year) 0. 8 -19 -

Power Penalty to Fix EM with AVS 17. 00 Core Power (m. W) P/G Power (m. W) 14% power penalty 0. 35 16. 00 Least invested guardband 15. 00 Highest 14. 00 invested guardband 13. 00 1 2 3 4 5 6 Implemetation # 7 8 0. 35 0. 34 0. 33 0. 32 0. 31 P/G Power (m. W) Core Power (m. W) • Core power increases due to elevated voltage • P/G power increases due to both elevated voltage and mesh degradation • A tradeoff between invested guardband in signoff -20 -

EM Impact on AVS Scheduling n n AVS behavior is an important role to decide the EM penalty on lifetime We empirically sweep AVS voltage step size to obtain the impact – – n #Implementation 3 is used AVS starts at 0. 9 V, and no EM fix for AVS in signoff 5 step sizes – – – S 1 = 8 m. V S 2 = 10 m. V S 3 = 15 m. V S 4 = 18 m. V S 5 = 20 m. V -21 -

EM Impact on AVS Scheduling 1. 04 1. 02 1. 00 0. 98 0. 96 0. 94 0. 92 0. 90 S 2 DMA, #3 0 2 S 3 MTTF (Year) VDD S 1 S 4 1. 2 years MTTF penalty 8. 1 8. 0 7. 9 S 1 4 S 5 6 Year S 2 8 S 3 S 4 10 S 5 12 -22 -

Outline n n Motivation Previous Work n Analysis Models Experimental Setup and Results n Conclusions n -23 -

Conclusions n n n We study the joint impact of BTI, AVS and EM on signoff We study two EM models and their impact on implementation (i) Black’s Equation and (ii) Mishra. Sapatnekar We demonstrate empirical results for lifetime, area and power penalty due to EM when AVS is involved – Up to 30% lifetime penalty n We demonstrate empirical results for power at different signoff corners – Up to 14% power penalty n Ongoing – Improve accuracy of signoff using a temperature gradient – Learning-based modeling to quantify design costs of reliability -24 -

Thank you! -25 -

Backup -26 -

EM Model: Mishra-Sapatnekar Log-normal distribution -27 -

Study on EM Impact in AVS System n n n Assume two types of degradation IR drop due to power mesh degradation (∆RPG due to EM) Signal wire degradation due to EM Vregulator ∆RPG (due to EM) Mesh and ring Core (VDD domain) -28 -