Chapter One Introduction to Pipelined Processors Principle of

Chapter One Introduction to Pipelined Processors

Principle of Designing Pipeline Processors (Design Problems of Pipeline Processors)

Job Sequencing and Collision Prevention

Job Sequencing and Collision Prevention • Consider reservation table given below at t=0 0 Sa Sb Sc 1 2 3 4 A 5 A A A

Job Sequencing and Collision Prevention • Consider next initiation made at t=1 0 1 2 3 4 5 6 Sa A 1 A 2 Sb A 1 A 2 Sc A 1 A 2 7 • The second initiation easily fits in the reservation table

Job Sequencing and Collision Prevention • Now consider the case when first initiation is made at t = 0 and second at t = 2. 0 1 2 Sa A 1 A 2 Sb Sc A 1 A 2 A 1 3 4 A 1 A A 2 2 A 2 5 6 7 A 1 A 2 A 1 A 2 • Here both markings A 1 and A 2 falls in the same stage time units and is called collision and it must be avoided

Terminologies

Terminologies • Latency: Time difference between two initiations in units of clock period • Forbidden Latency: Latencies resulting in collision • Forbidden Latency Set: Set of all forbidden latencies

General Method of finding Latency Considering all initiations: 0 1 2 3 4 5 6 7 8 9 10 S A 6 A a A 1 A 2 A 3 A 4 A 5 A 6 1 S A 1 A A 2 A A 3 A A 4 A b A 1 A 2 3 A 5 A 6 4 5 6 • Forbidden Latencies 2 and A 1 A are A 2 A A 3 A 5 A 4 A Sc A 1 A 2 A 5 A 6 3 4 5 6

Shortcut Method of finding Latency • Forbidden Latency Set = {0, 5} U {0, 2} = { 0, 2, 5 }

Terminologies • Initiation Sequence : Sequence of time units at which initiation can be made without causing collision • Example : { 0, 1, 3, 4 …. } • Latency Sequence : Sequence of latencies between successive initiations • Example : { 1, 2, 1…. } • For a RT, number of valid initiations and latencies are infinite

Terminologies • Initiation Rate : – The average number of initiations done per unit time – It is a positive fraction and maximum value of IR is 1 • Average Latency : The average of latency of a given latency sequence AL = 1/IR

Terminologies • Latency Cycle: • Among the infinite possible latency sequence, the periodic ones are significant. E. g. { 1, 3, 3, … } • The subsequence that repeats itself is called latency cycle. E. g. {1, 3, 3}

Terminologies • Period of cycle: The sum of latencies in a latency cycle (1+3+3=7) • Average Latency: The average taken over its latency cycle (AL=7/3=2. 33) • To design a pipeline, we need a control strategy that maximize throughput (no. of results per unit time) • Maximizing throughput is minimizing AL

Terminologies • Control Strategy – Initiate pipeline as specified by latency sequence. – Latency sequence which is aperiodic in nature is impossible to design • Thus design problem is arriving at a latency cycle having minimal average latency.

Terminologies • Stage Utilization Factor (SUF): • SUF of a particular stage is the fraction of time units the stage used while following a latency sequence. • Example: Consider 5 initiations of function A as below 0 1 Sa A 1 A 2 Sb Sc 2 3 4 5 6 7 A 3 A 1 A 2 A 4 A 1 A 2 A 3 A 3 8 9 10 11 12 13 A A 4 A 5 5 A 3 A 4 A 5

Terminologies • SUF of stage Sa is number of markings present along Sa divided by the time interval over which marking is counted. • SUF(Sa) = SUF(Sb) = SUF(Sc) = 10/14

Terminologies • Let SU(i) be the stage utilization factor of stage i • Let N(i) be no. of markings against stage i in the reservation table • Suppose we initiate pipeline with initiation rate (IR), then SU(i) is given by

SUF 0 1 Sa A 1 A 2 Sb Sc 2 3 4 5 6 7 A 3 A 1 A 2 A 4 A 1 A 2 A 3 A 3 8 9 10 11 12 13 A A 4 A 5 5 A 3 A 4 A 5

Terminologies • Minimum Average Latency (MAL) • Thus SU(i) = IR x N(i) • SU(i) ≤ 1 IR x N(i) ≤ 1/IR N(i) ≤ AL • Therefore

State Diagram • Suppose a pipeline is initially empty and make an initiation at t = 0. • Now we need to check whether an initiation possible at t = i for i > 0. • bi is used to note possibility of initiation • bi = 1 initiation not possible • bi = 0 initiation possible

State Diagram bi 1 0 0 1

State Diagram • The above binary representation (binary vector) is called collision vector(CV) • The collision vector obtained after making first initiation is called initial collision vector(ICV) ICVA = (101001) • The graphical representation of states (CVs) that a pipeline can reach and the relation is given by state diagram

State Diagram • States (CVs) are denoted by nodes • The node representing CVt-1 is connected to CVt by a directed graph from CVt-1 to CVt and similarly for CVt* with a * on arc

Procedure to draw state diagram 1. Start with ICV 2. For each unprocessed state, say CVt-1, do as follows: a) Find CVt from CVt-1 by the following steps 1. Left shift CVt-1 by 1 bit 2. Drop the leftmost bit 3. Append the bit 0 at the right-hand end

Procedure to draw state diagram b) If the 0 th bit of CVt is 0, then obtain CV* by logically ORing CVt with ICV. c) Make a new node for CVt and join with CVt-1 with an arc if the state CVt does not already exist. d) If CV* exists, repeat step (c), but mark the arc with a *.