Pipelined Datapath and Control Lecture for CPSC 5155

Pipelined Datapath and Control Lecture for CPSC 5155 Edward Bosworth, Ph. D. Computer Science Department Columbus State University

§ 4. 6 Pipelined Datapath and Control MIPS Pipelined Datapath MEM Right-to-left flow leads to hazards WB Chapter 4 — The Processor — 2

Pipeline registers n Need registers between stages n To hold information produced in previous cycle Chapter 4 — The Processor — 3

The Pipeline Registers • IF/ID This provides an execution context for the ID (Instruction Decode and Register Fetch) stage of execution. • ID/EX This provides an execution context for the EX (Execute) phase of instruction execution. In particular, the discrete control signals generated by the control unit as a result of instruction decoding are stored here. • EX/MEM This provides an execution context for the MEM (Memory Access or R-Type Instruction Completion) phase of instruction execution. In addition , this register stores copies of the control signals required to complete both the MEM and WB phase of execution for this instruction. • MEM/WB This provides an execution context for the WB (Write Back) phase of instruction execution.

Pipeline Operation n Cycle-by-cycle flow of instructions through the pipelined datapath n “Single-clock-cycle” pipeline diagram n n n c. f. “multi-clock-cycle” diagram n n Shows pipeline usage in a single cycle Highlight resources used Graph of operation over time We’ll look at “single-clock-cycle” diagrams for load & store Chapter 4 — The Processor — 5

IF for Load, Store, … Chapter 4 — The Processor — 6

ID for Load, Store, … Chapter 4 — The Processor — 7

EX for Load Chapter 4 — The Processor — 8

MEM for Load Chapter 4 — The Processor — 9

WB for Load Wrong register number Chapter 4 — The Processor — 10

Corrected Datapath for Load Chapter 4 — The Processor — 11

EX for Store Chapter 4 — The Processor — 12

MEM for Store Chapter 4 — The Processor — 13

WB for Store Chapter 4 — The Processor — 14

Multi-Cycle Pipeline Diagram n Form showing resource usage Chapter 4 — The Processor — 15

Multi-Cycle Pipeline Diagram n Traditional form Chapter 4 — The Processor — 16

Single-Cycle Pipeline Diagram n State of pipeline in a given cycle Chapter 4 — The Processor — 17

Pipelined Control (Simplified) Chapter 4 — The Processor — 18

Pipelined Control n Control signals derived from instruction n As in single-cycle implementation Chapter 4 — The Processor — 19

The Control Signals by Phase • Instruction Fetch There are no control signals specific to this stage. • Instruction Decode There are no instruction–specific control signals in this step. • Execute • There are three control signals associated with this step. • Reg. Dst This selects which field, IR[20: 16] or IR[15: 11] will be used as the register destination number for the Write Register in WB. The five bit value selected is written into EX/MEM and copied to MEM/WB. • ALUOp This is the two–bit selector of the ALU operation. • ALUSrc This discrete control signal selects the B input to the ALU.

Control Signals by Phase • • • Memory Access There are three control signals associated with this step. Branch This indicates that a branch instruction is in this stage. Mem. Read The ALU output is used as a memory address that is read. This is set by the LW instruction. Mem. Write The ALU output is used as a memory address, to which the contents of the specified register are written. This is set by the SW instruction. Write Back There are two control signals associated with this step. Mem. To. Reg This selects either the ALU output or memory output to be written back to the register file Reg. Write This causes the selected value to be written to the specified register.

Pipelined Control Chapter 4 — The Processor — 22

Size of the Pipeline Registers Program Counter Machine Language Instruction Register 1 Read Data Register 2 Read Data Sign Extended Address Offset Discrete Control Signals ALU Function Code Shift Amount ALU Result ALU Discrete Output: Zero Data read from memory Destination Register Number TOTAL BITS IF/ID 32 32 64 ID/EX 32 32 32 9 6 5 10 158 EX/MEM 32 32 5 32 1 5 107 MEM/WB 32 2 32 5 103

n Consider this sequence: sub and or add sw n $2, $1, $3 $12, $5 $13, $6, $2 $14, $2 $15, 100($2) We can resolve hazards with forwarding n § 4. 7 Data Hazards: Forwarding vs. Stalling Data Hazards in ALU Instructions How do we detect when to forward? Chapter 4 — The Processor — 24

Dependencies & Forwarding Chapter 4 — The Processor — 25

Detecting the Need to Forward n Pass register numbers along pipeline n n ALU operand register numbers in EX stage are given by n n e. g. , ID/EX. Register. Rs = register number for Rs sitting in ID/EX pipeline register ID/EX. Register. Rs, ID/EX. Register. Rt Data hazards when 1 a. EX/MEM. Register. Rd = ID/EX. Register. Rs 1 b. EX/MEM. Register. Rd = ID/EX. Register. Rt 2 a. MEM/WB. Register. Rd = ID/EX. Register. Rs 2 b. MEM/WB. Register. Rd = ID/EX. Register. Rt Fwd from EX/MEM pipeline reg Fwd from MEM/WB pipeline reg Chapter 4 — The Processor — 26

Detecting the Need to Forward n But only if forwarding instruction will write to a register! n n EX/MEM. Reg. Write, MEM/WB. Reg. Write And only if Rd for that instruction is not $zero n EX/MEM. Register. Rd ≠ 0, MEM/WB. Register. Rd ≠ 0 Chapter 4 — The Processor — 27

Forwarding Paths Chapter 4 — The Processor — 28

Forwarding Conditions n EX hazard n n n if (EX/MEM. Reg. Write and (EX/MEM. Register. Rd ≠ 0) and (EX/MEM. Register. Rd = ID/EX. Register. Rs)) Forward. A = 10 #Two bit control signal to MUX if (EX/MEM. Reg. Write and (EX/MEM. Register. Rd ≠ 0) and (EX/MEM. Register. Rd = ID/EX. Register. Rt)) Forward. B = 10 MEM hazard n n if (MEM/WB. Reg. Write and (MEM/WB. Register. Rd ≠ 0) and (MEM/WB. Register. Rd = ID/EX. Register. Rs)) Forward. A = 01 if (MEM/WB. Reg. Write and (MEM/WB. Register. Rd ≠ 0) and (MEM/WB. Register. Rd = ID/EX. Register. Rt)) Forward. B = 01 Chapter 4 — The Processor — 29

Double Data Hazard n Consider the sequence: add $1, $2 add $1, $3 add $1, $4 n Both hazards occur n n Want to use the most recent Revise MEM hazard condition n Only fwd if EX hazard condition isn’t true Chapter 4 — The Processor — 30

Revised Forwarding Condition n MEM hazard n n if (MEM/WB. Reg. Write and (MEM/WB. Register. Rd ≠ 0) and not (EX/MEM. Reg. Write and (EX/MEM. Register. Rd ≠ 0) and (EX/MEM. Register. Rd = ID/EX. Register. Rs)) and (MEM/WB. Register. Rd = ID/EX. Register. Rs)) Forward. A = 01 if (MEM/WB. Reg. Write and (MEM/WB. Register. Rd ≠ 0) and not (EX/MEM. Reg. Write and (EX/MEM. Register. Rd ≠ 0) and (EX/MEM. Register. Rd = ID/EX. Register. Rt)) and (MEM/WB. Register. Rd = ID/EX. Register. Rt)) Forward. B = 01 Chapter 4 — The Processor — 31

Datapath with Forwarding Chapter 4 — The Processor — 32

Load-Use Data Hazard Need to stall for one cycle Chapter 4 — The Processor — 33

Load-Use Hazard Detection n n Check when using instruction is decoded in ID stage ALU operand register numbers in ID stage are given by n n Load-use hazard when n n IF/ID. Register. Rs, IF/ID. Register. Rt ID/EX. Mem. Read and ((ID/EX. Register. Rt = IF/ID. Register. Rs) or (ID/EX. Register. Rt = IF/ID. Register. Rt)) If detected, stall and insert bubble Chapter 4 — The Processor — 34

How to Stall the Pipeline n Force control values in ID/EX register to 0 n n EX, MEM and WB do nop (no-operation) Prevent update of PC and IF/ID register n n n Using instruction is decoded again Following instruction is fetched again 1 -cycle stall allows MEM to read data for lw n Can subsequently forward to EX stage Chapter 4 — The Processor — 35

Stall/Bubble in the Pipeline Stall inserted here Chapter 4 — The Processor — 36

Stalls and Performance The BIG Picture n Stalls reduce performance n n But are required to get correct results Compiler can arrange code to avoid hazards and stalls n Requires knowledge of the pipeline structure Chapter 4 — The Processor — 37