EE 4271 VLSI Design Professor Shiyan Hu Office

EE 4271 VLSI Design Professor Shiyan Hu Office: EERC 518 shiyan@mtu. edu The Inverter Adapted and modified from Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic. © Digital Integrated Circuits 2 nd Inverter

Pass-Transistors q q Need a circuit element which acts as a switch When the control signal CLK is high, Vout=Vin When the control signal CLK is low, Vout is open circuited We can use NMOS or PMOS to implement it. For PMOS device, the polarity of CLK is reversed. NMOS based PMOS based © Digital Integrated Circuits 2 nd Inverter

NMOS Pass Transistors q q q Initially Vout=0. input=drain, output=source When CLK=0, then Vgs=0. NMOS cut-off When CLK=Vdd, q If Vin=Vdd (Vout=0 initially), Vgs>Vt, Vgs-Vt=Vdd-Vt<=Vds=Vdd, NMOS is in saturation region as a transient response and CL is charged. q When Vout reaches Vdd-Vt, Vgs=Vdd-(Vdd-Vt)=Vt. NMOS cut-off. q However, if Vout drops below Vdd-Vt, NMOS will be turned on again since Vgs>Vt. q Thus, NMOS transmits Vdd value but drops it by Vt. © Digital Integrated Circuits 2 nd Inverter

NMOS Pass Transistors - II q If Vin=0 (and CLK=Vdd), source=input, drain=output q If Vout=Vdd-Vt (note that it is the maximum value for Vout for the transistor to be on), Vgs=Vdd>Vt, Vds=Vdd. Vt=Vgs-Vt q The NMOS is on the boundary of linear region and saturation region q CL is discharged q As Vout approaches 0, the NMOS is linear region. Thus, Vout is completely discharged. q When Vout=0, Vds=0 and Ids=0, thus, the discharge is done. q NMOS pass transistor transmits a 0 voltage without any degradation © Digital Integrated Circuits 2 nd Inverter

PMOS Pass Transistors q q Similar to NMOS pass transistor Assume that initially Vout=0 When CLK=Vdd, PMOS cut-off When CLK=0, q If Vin=Vdd, PMOS transmits a Vdd value without degradation q If Vin=0, PMOS transmits a 0 value with degradation, Vout=|Vt| © Digital Integrated Circuits 2 nd Inverter

Transmission Gate q q q An NMOS transmits a 0 value without degradation while transmits a Vdd value with degradation A PMOS transmits a Vdd value without degradation while transmits a 0 value with degradation Use both in parallel, then can transmit both 0 and Vdd well. CLK=0, both transistors cut-off CLK=Vdd, both transistors are on. When Vin=Vdd, NMOS cut-off when Vout=Vdd-Vtn, but PMOS will drag Vout to Vdd. When Vin=0, PMOS cut-off when Vout=|Vtp|, but NMOS will drag Vout to 0. © Digital Integrated Circuits 2 nd Inverter

Propagation Delay © Digital Integrated Circuits 2 nd Inverter

Rising delay and Falling delay q Rising delay tr=time for the signal to change from 10% to 90% of Vdd q Falling delay tf=time for the signal to change from 90% to 10% of Vdd q Delay=time from input signal transition (50% Vdd) to output signal transition (50% Vdd). © Digital Integrated Circuits 2 nd Inverter

Delay © Digital Integrated Circuits 2 nd Inverter

Inverter falling-time © Digital Integrated Circuits 2 nd Inverter

NMOS falling time For NMOS VDD S Vin D D 1. Vin=0, Vgsn=0<Vt, Vdsn=Vout=Vdd, NMOS is in cut-off region, X 1 2. Vin=Vdd, instantaneously, Vgsn=Vdd>Vt, Vdsn=Vout=Vdd, Vgsn. Vtn=Vdd-Vtn<Vdd, NMOS is in saturation region, X 2 3. The operating point follows the arrow to the origin. So Vout=0 at X 3. Vout CL S © Digital Integrated Circuits 2 nd Inverter

NMOS falling time q q q tf 1 tf 2 © Digital Integrated Circuits 2 nd q When Vin=Vdd, instantaneously, Vgsn=Vdd tf=tf 1+tf 2 tf 1: time for the voltage on CL to switch from 0. 9 Vdd to Vgsn. Vtn=Vdd-Vtn tf 2: time for the voltage on CL to switch from Vdd-Vtn to 0. 1 Vdd Inverter

NMOS falling time q For Vdsn=Vout tf 1: q Integrate Vgsn=Vdd Vout from 0. 9 Vdd to Vdd-Vt tf 2, we have © Digital Integrated Circuits 2 nd Inverter

NMOS falling time q tf=tf 1+tf 2 q Assume Vt=0. 2 Vdd © Digital Integrated Circuits 2 nd Inverter

Rising time q Assume |Vtp|=0. 2 Vdd © Digital Integrated Circuits 2 nd Inverter

Falling and Rising time q Assume Vtn=-Vtp, then we can show that q Thus, for equal rising and falling time, set q That is, Wp=2 Wn since up=un/2 © Digital Integrated Circuits 2 nd Inverter

Power Dissipation © Digital Integrated Circuits 2 nd Inverter

Where Does Power Go in CMOS? © Digital Integrated Circuits 2 nd Inverter

Dynamic Power Dissipation Vdd Vin Vout CL Power = CL * Vdd 2 * f Not a function of transistor sizes Need to reduce CL, Vdd, and f to reduce power. © Digital Integrated Circuits 2 nd Inverter

Dynamic Power Dynamic power is due to charging/discharging load capacitor CL In charging, CL is loaded with a charge CL Vdd which requires the energy of QVdd= CL Vdd 2, and all the energy will be dissipated when discharging is done. Total power = CL Vdd 2 If this is performed with frequency f, clearly, total power = CL Vdd 2 f © Digital Integrated Circuits 2 nd Inverter

Dynamic Power- II q q q If the waveform is not periodic, denote by P the probability of switching for the signal The dynamic power is the most important power source It is quadratically dependant on Vdd It is proportional to the number of switching. We can slow down the clock not on the timing critical path to save power. It is not dependent of the transistor itself but the load of the transistor. © Digital Integrated Circuits 2 nd Inverter

Short Circuit Currents Happens when both transistors are on. If every switching is instantaneous, then no short circuits. Longer delay -> larger short circuit power © Digital Integrated Circuits 2 nd Inverter

Short-Circuit Currents © Digital Integrated Circuits 2 nd Inverter

Leakage Sub-threshold current is one of most compelling issues in low-energy circuit design. © Digital Integrated Circuits 2 nd Inverter

Subthreshold Leakage Component © Digital Integrated Circuits 2 nd Inverter

Principles for Power Reduction q Prime choice: Reduce voltage § Recent years have seen an acceleration in supply voltage reduction § Design at very low voltages still open question (0. 5 V) q Reduce switching activity q Reduce physical capacitance © Digital Integrated Circuits 2 nd Inverter

Impact of Technology Scaling © Digital Integrated Circuits 2 nd Inverter

Goals of Technology Scaling q Make things cheaper: § Want to sell more functions (transistors) per chip for the same money § Build same products cheaper, sell the same part for less money § Price of a transistor has to be reduced q But also want to be faster, smaller, lower power © Digital Integrated Circuits 2 nd Inverter

Scaling q Goals of scaling the dimensions by 30%: § Reduce gate delay by 30% § Double transistor density q Die size used to increase by 14% per generation q Technology generation spans 2 -3 years © Digital Integrated Circuits 2 nd Inverter

Technology Scaling q q Devices scale to smaller dimensions with advancing technology. A scaling factor S describes the ratio of dimension between the old technology and the new technology. In practice, S=1. 2 -1. 5. © Digital Integrated Circuits 2 nd Inverter

Technology Scaling - II q q q In practice, it is not feasible to scale voltage since different ICs in the system may have different Vdd. This may require extremely complex additional circuits. We can only allow very few different levels of Vdd. In technology scaling, we often have fixed voltage scaling model. W, L, tox scales down by 1/S Vdd, Vt unchanged Area scales down by 1/S 2 Cox scales up by S due to tox Gate capacitance = Cox. WL scales down by 1/S scales up by S Linear and saturation region current scales up by S Current density scales up by S 3 P=Vdd*I, power density scales up by S 3 Power consumption is a major design issue © Digital Integrated Circuits 2 nd Inverter

Summary q Inverter § Five regions Transmission gate q Inverter delay q Power q § Dynamic § Leakage § Short-circuit q Technology scaling © Digital Integrated Circuits 2 nd Inverter