EE 4271 VLSI Design Fall 2011 CMOS Combinational

EE 4271 VLSI Design, Fall 2011 CMOS Combinational Gate

CMOS Combinational Circuits • Implementation of logic gates and other structures using CMOS technology. • Basic element: transistor • 2 types of transistors: – n-channel (n. MOS) and p-channel (p. MOS) – Type depends on the semiconductor materials used to implement the transistor. – We want to model transistor behavior at the logic level in order to study the behavior of CMOS circuits view p. MOS and n. MOS transistors as swithes. 26 -Sep-20 Combinational Logic PJF - 2

CMOS transistors as Switches 3 terminals in CMOS transistors: § G: Gate § D: Drain § S: Source n. MOS transistor/switch X=1 switch closes (ON) X=0 switch opens (OFF) 26 -Sep-20 Combinational Logic p. MOS transistor/switch X=1 switch opens (OFF) X=0 switch closes (ON) PJF - 3

Networks of Switches • Use switches to create networks that represent CMOS logic circuits. • To implement a function F, create a network s. t. there is a path through the network whenever F=1 and no path when F=0. • Two basic structures: – Transistors in Series – Transistors in Parallel 26 -Sep-20 Combinational Logic PJF - 4

Transistors in Series/Parallel n. MOS in Series X a Y a X: X Y: Y b n. MOS in Parallel Path between points a and b exists if both X and Y are 1 X • Y a X X Y X: X’ Y: Y’ b 26 -Sep-20 a X: X b b Y: Y b Path between points a and b exists if either X or Y are 1 X+Y p. MOS in Parallel p. MOS in Series a Y a Path between points a and b exists if both X and Y are 0 X’ • Y’ b Combinational Logic a X Y a X: X b Y: Y Path between points a and b exists if either X or Y are 0 X’+Y’ b PJF - 5

Networks of Switches (cont. ) In general: • 1. 2. 3. 4. n. MOS in series is used to implement AND logic p. MOS in series is used to implement NOR logic n. MOS in parallel is used to implement OR logic p. MOS in parallel is used to implement NAND logic Observe that: • – – 26 -Sep-20 1 is the complement of 4, and vice-versa 2 is the complement of 3, and vice-versa Combinational Logic PJF - 6

CMOS Inverter +V X F = X’ Logic symbol GRD Transistor-level schematic Operation: q X=1 n. MOS switch conducts (p. MOS is open) and draws from GRD F=0 q X=0 p. MOS switch conducts (n. MOST is open) and draws from +V F=1 26 -Sep-20 Combinational Logic PJF - 7

Fully Complementary CMOS Networks Basic Gates 26 -Sep-20 Combinational Logic PJF - 8

Fully Complementary CMOS Complex Gates Given a function F: 1. First take the complement of F to form F’ 2. Implement F’ as an n. MOS net and connect it to GRD (pulldown net) and F. 3. Find dual of F’, implement it as a p. MOS net and connect it to +V (pull-up net) and F. 4. Connect switch inputs. 26 -Sep-20 Combinational Logic PJF - 9