Introduction to CMOS VLSI Design Interconnect 1 Outline

Introduction to CMOS VLSI Design Interconnect 1

Outline q q q q Introduction Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters Interconnect CMOS VLSI Design 2

Introduction q Chips are mostly made of wires called interconnect – In stick diagram, wires set size – Transistors are little things under the wires – Many layers of wires q Wires are as important as transistors – Speed – Power – Noise q Alternating layers run orthogonally Interconnect CMOS VLSI Design 3

Wire Geometry q Pitch = w + s q Aspect ratio: AR = t/w – Old processes had AR << 1 – Modern processes have AR 2 • Pack in many skinny wires Interconnect CMOS VLSI Design 4

Layer Stack q AMI 0. 6 mm process has 3 metal layers q Modern processes use 6 -10+ metal layers q Example: Intel 180 nm process q M 1: thin, narrow (< 3 l) – High density cells q M 2 -M 4: thicker – For longer wires q M 5 -M 6: thickest – For VDD, GND, clk Interconnect CMOS VLSI Design 5

Wire Resistance q r = resistivity (W*m) Interconnect CMOS VLSI Design 6

Wire Resistance q r = resistivity (W*m) Interconnect CMOS VLSI Design 7

Wire Resistance q r = resistivity (W*m) q R = sheet resistance (W/ ) – is a dimensionless unit(!) q Count number of squares – R = R * (# of squares) Interconnect CMOS VLSI Design 8

Choice of Metals q Until 180 nm generation, most wires were aluminum q Modern processes often use copper – Cu atoms diffuse into silicon and damage FETs – Must be surrounded by a diffusion barrier Metal Bulk resistivity (m. W*cm) Silver (Ag) 1. 6 Copper (Cu) 1. 7 Gold (Au) 2. 2 Aluminum (Al) 2. 8 Tungsten (W) 5. 3 Molybdenum (Mo) 5. 3 Interconnect CMOS VLSI Design 9

Sheet Resistance q Typical sheet resistances in 180 nm process Layer Sheet Resistance (W/ ) Diffusion (silicided) 3 -10 Diffusion (no silicide) 50 -200 Polysilicon (silicided) 3 -10 Polysilicon (no silicide) 50 -400 Metal 1 0. 08 Metal 2 0. 05 Metal 3 0. 05 Metal 4 0. 03 Metal 5 0. 02 Metal 6 0. 02 Interconnect CMOS VLSI Design 10

Contacts Resistance q Contacts and vias also have 2 -20 W q Use many contacts for lower R – Many small contacts for current crowding around periphery Interconnect CMOS VLSI Design 11

Wire Capacitance q Wire has capacitance per unit length – To neighbors – To layers above and below q Ctotal = Ctop + Cbot + 2 Cadj Interconnect CMOS VLSI Design 12

Capacitance Trends q Parallel plate equation: C = e. A/d – Wires are not parallel plates, but obey trends – Increasing area (W, t) increases capacitance – Increasing distance (s, h) decreases capacitance q Dielectric constant – e = ke 0 q e 0 = 8. 85 x 10 -14 F/cm q k = 3. 9 for Si. O 2 q Processes are starting to use low-k dielectrics – k 3 (or less) as dielectrics use air pockets Interconnect CMOS VLSI Design 13

M 2 Capacitance Data q Typical wires have ~ 0. 2 f. F/mm – Compare to 2 f. F/mm for gate capacitance Interconnect CMOS VLSI Design 14

Diffusion & Polysilicon q Diffusion capacitance is very high (about 2 f. F/mm) – Comparable to gate capacitance – Diffusion also has high resistance – Avoid using diffusion runners for wires! q Polysilicon has lower C but high R – Use for transistor gates – Occasionally for very short wires between gates Interconnect CMOS VLSI Design 15

Lumped Element Models q Wires are a distributed system – Approximate with lumped element models q 3 -segment p-model is accurate to 3% in simulation q L-model needs 100 segments for same accuracy! q Use single segment p-model for Elmore delay Interconnect CMOS VLSI Design 16

Example q Metal 2 wire in 180 nm process – 5 mm long – 0. 32 mm wide q Construct a 3 -segment p-model – R = – Cpermicron = Interconnect CMOS VLSI Design 17

Example q Metal 2 wire in 180 nm process – 5 mm long – 0. 32 mm wide q Construct a 3 -segment p-model – R = 0. 05 W/ => R = 781 W – Cpermicron = 0. 2 f. F/mm => C = 1 p. F Interconnect CMOS VLSI Design 18

Wire RC Delay q Estimate the delay of a 10 x inverter driving a 2 x inverter at the end of the 5 mm wire from the previous example. – R = 2. 5 k. W*mm for gates – Unit inverter: 0. 36 mm n. MOS, 0. 72 mm p. MOS – tpd = Interconnect CMOS VLSI Design 19

Wire RC Delay q Estimate the delay of a 10 x inverter driving a 2 x inverter at the end of the 5 mm wire from the previous example. – R = 2. 5 k. W*mm for gates – Unit inverter: 0. 36 mm n. MOS, 0. 72 mm p. MOS – tpd = 1. 1 ns Interconnect CMOS VLSI Design 20

Crosstalk q A capacitor does not like to change its voltage instantaneously. q A wire has high capacitance to its neighbor. – When the neighbor switches from 1 -> 0 or 0 ->1, the wire tends to switch too. – Called capacitive coupling or crosstalk. q Crosstalk effects – Noise on nonswitching wires – Increased delay on switching wires Interconnect CMOS VLSI Design 21

Crosstalk Delay q Assume layers above and below on average are quiet – Second terminal of capacitor can be ignored – Model as Cgnd = Ctop + Cbot q Effective Cadj depends on behavior of neighbors – Miller effect DV B Ceff(A) MCF Constant Switching with A Switching opposite A Interconnect CMOS VLSI Design 22

Crosstalk Delay q Assume layers above and below on average are quiet – Second terminal of capacitor can be ignored – Model as Cgnd = Ctop + Cbot q Effective Cadj depends on behavior of neighbors – Miller effect B DV Ceff(A) MCF Constant VDD Cgnd + Cadj 1 Switching with A 0 Cgnd 0 Switching opposite A 2 VDD Cgnd + 2 Cadj 2 Interconnect CMOS VLSI Design 23

Crosstalk Noise q Crosstalk causes noise on nonswitching wires q If victim is floating: – model as capacitive voltage divider Interconnect CMOS VLSI Design 24

Driven Victims q Usually victim is driven by a gate that fights noise – Noise depends on relative resistances – Victim driver is in linear region, agg. in saturation – If sizes are same, Raggressor = 2 -4 x Rvictim Interconnect CMOS VLSI Design 25

Coupling Waveforms q Simulated coupling for Cadj = Cvictim Interconnect CMOS VLSI Design 26

Noise Implications q So what if we have noise? q If the noise is less than the noise margin, nothing happens q Static CMOS logic will eventually settle to correct output even if disturbed by large noise spikes – But glitches cause extra delay – Also cause extra power from false transitions q Dynamic logic never recovers from glitches q Memories and other sensitive circuits also can produce the wrong answer Interconnect CMOS VLSI Design 27

Wire Engineering q Goal: achieve delay, area, power goals with acceptable noise q Degrees of freedom: Interconnect CMOS VLSI Design 28

Wire Engineering q Goal: achieve delay, area, power goals with acceptable noise q Degrees of freedom: – Width – Spacing Interconnect CMOS VLSI Design 29

Wire Engineering q Goal: achieve delay, area, power goals with acceptable noise q Degrees of freedom: – Width – Spacing – Layer Interconnect CMOS VLSI Design 30

Wire Engineering q Goal: achieve delay, area, power goals with acceptable noise q Degrees of freedom: – Width – Spacing – Layer – Shielding Interconnect CMOS VLSI Design 31

Repeaters q R and C are proportional to l q RC delay is proportional to l 2 – Unacceptably great for long wires Interconnect CMOS VLSI Design 32

Repeaters q R and C are proportional to l q RC delay is proportional to l 2 – Unacceptably great for long wires q Break long wires into N shorter segments – Drive each one with an inverter or buffer Interconnect CMOS VLSI Design 33

Repeater Design q How many repeaters should we use? q How large should each one be? q Equivalent Circuit – Wire length l/N • Wire Capaitance Cw*l/N, Resistance Rw*l/N – Inverter width W (n. MOS = W, p. MOS = 2 W) • Gate Capacitance C’*W, Resistance R/W Interconnect CMOS VLSI Design 34

Repeater Design q How many repeaters should we use? q How large should each one be? q Equivalent Circuit – Wire length l • Wire Capacitance Cw*l, Resistance Rw*l – Inverter width W (n. MOS = W, p. MOS = 2 W) • Gate Capacitance C’*W, Resistance R/W Interconnect CMOS VLSI Design 35

Repeater Results q Write equation for Elmore Delay – Differentiate with respect to W and N – Set equal to 0, solve ~60 -80 ps/mm in 180 nm process Interconnect CMOS VLSI Design 36