Chapter 7 Programmable ASIC Interconnect ApplicationSpecific Integrated Circuits

Chapter 7 Programmable ASIC Interconnect Application-Specific Integrated Circuits Michael John Sebastian Smith Addison Wesley, 1997 EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits , Michael John Sebastian Smith, Addison Wesley, 1997

Programmable Interconnect l l l In addition to programmable cells, programmable ASICs must have programmable interconnect to connect cells together form logic function Structure and complexity of the interconnect is determined primarily by the programming technology and architecture of the basic cell Interconnect is typically done on aluminum-based metal layers n n l Resistance of approximately 50 m. W/square Line capacitance of approximately 0. 2 p. F/cm Early programmable ASICs had two metal interconnect layers, but current, high density parts may have three or more metal layers EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits , Michael John Sebastian Smith, Addison Wesley, 1997

Actel Programmable Interconnect l Actel interconnect is similar to a channeled gate array n n l l Each channel has a fixed number of tracks each of which holds one wire Wires in track are divided into segments of various lengths segmented channel routing Long vertical tracks (LVT) extend the entire height of the chip Each logic module has connections to its inputs and outputs called stubs n n l Horizontal routing channels between rows of logic modules Vertical routing channels on top of cells Input stubs extend vertically into routing channels above and below logic module Output stub extends vertically 2 channels up and 2 channels down Wires are connected by antifuses EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits , Michael John Sebastian Smith, Addison Wesley, 1997

Actel Programmable Interconnect Figure 7. 1 The interconnect architecture used in an Actel ACT family FPGA. EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits , Michael John Sebastian Smith, Addison Wesley, 1997

Detail of ACT 1 Channel Architecture Figure 7. 2 ACT 1 horizontal and vertical channel architecture. EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits , Michael John Sebastian Smith, Addison Wesley, 1997

Elmore’s Constant l Approximation of waveform at node i: where Rki is the resistance of the path to V 0 shared by node k and node i l Examples: R 24 = R 1, R 22 = R 1+R 2, and R 31 = R 1 l If the switching points are assumed to be at the 0. 35 and 0. 65 points, the delay at node i can be approximated by t. DI Figure 7. 3 Measuring the delay of a net. (a) An RC tree. (b) The waveforms as a result of closing the switch at t=0. EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits , Michael John Sebastian Smith, Addison Wesley, 1997

RC Delay in Antifuse Connections l Rn - resistance of antifuse, Cn - capacitance of wire segment t. D 4 = R 14 C 1 + R 24 C 2 + R 34 C 3 + R 44 C 4 l = (R 1 + R 2 + R 3 + R 4)C 4 + (R 1 + R 2 + R 3)C 3 + (R 1 + R 2)C 2 + R 1 C 1 If all antifuse resistances are approximately equal and much larger than the resistance of the wire segment, then: R 1 = R 2 = R 3 = R 4, and: t. D 4 = 4 RC 4 + 3 RC 3 + 2 RC 2 + RC 1 l l A connection with two antifuses will generate a 3 RC time constant, a connection with three antifuses will generate a 6 RC time constant, and a connection with 4 antifuses will generate a 10 RC time constant Interconnect delay grows quadratically (µ n 2) as the number of antifuses n increases Figure 7. 4 Actel routing model. (a) A four-antifuse connection. L 0 is an output stub, L 1 and L 3 are horizontal tracks, L 2 is a long vertical track (LVT), and L 4 is an output stub. (b) An RC-tree model. Each antifuse is modeled by a resistance and each interconnect segment is modeled by a capacitance. EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits , Michael John Sebastian Smith, Addison Wesley, 1997

Xilinx LCA Interconnect l Xilinx LCA interconnect has a hierarchical architecture: n n n Vertical lines and horizontal lines run between CLBs General-purpose interconnect joins switch boxes (also known as magic boxes or switching matrices) Long lines run across the entire chip - can be used to form internal buses using the three-state buffers that are next to each CLB Direct connections bypass the switch matrices and directly connect adjacent CLBs Programmable Interconnect Points (PIPs) are programmable pass transistors the connect CLB inputs and outputs to the routing network Bi-directional interconnect buffers (BIDI) restore the logic level and logic strength on long interconnect paths EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits , Michael John Sebastian Smith, Addison Wesley, 1997

Xilinx LCA Interconnect (cont. ) Figure 7. 5 Xilinx LCA interconnect. (a) The LCA architecture (notice the matrix element size is larger than a CLB). (b) A simplified representation of the interconnect resources. Each of the lines is a bus. EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits , Michael John Sebastian Smith, Addison Wesley, 1997

Xilinx Switching Matrix and Components of Interconnect Delay Figure 7. 6 Components of interconnect delay in a Xilinx LCA array. (a) A portion of the interconnect around the CLBs. (b) A switching matrix. (c) A detailed view inside the switching matrix showing the pass-transistor arrangement. (d) The equivalent circuit for the connection between nets 6 and 20 using the matrix. (e) A view of the interconnect at a Programmable Interconnection Point (PIP. (f) and (g) The equivalent schematic of a PIP connection (h) The complete RC delay path. EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits , Michael John Sebastian Smith, Addison Wesley, 1997

Xilinx EPLD Interconnect l l Xilinx EPLD family uses an interconnect bus called a Universal Interconnection Module (UIM) UIM is a programmable AND array with constant delay from any input to any output n n CG is the fixed gate capacitance of the EPROM device CD is the fixed drain capacitance of the EPROM device CB is the variable horizontal line capacitance CW is the variable vertical line capacitance Figure 7. 7 The Xilinx EPLD UIM (Universal Interconnection Module). (a) A simplified block diagram of the UIM. The UIM bus width, n, varies from 68 (XC 7236) to 198 (XC 73108). (b) The UIM is actually a large programmable AND array. (c) The parasitic capacitance of the EPROM cell. EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits , Michael John Sebastian Smith, Addison Wesley, 1997

Altera MAX 5000 and 7000 Interconnect l l Altera MAX 5000 and 7000 devices use a Programmable Interconnect Array (PIA) PIA is also a programmable AND array with constant delay from any input to any output Figure 7. 8 A simplified block diagram of the Altera MAX interconnect scheme. (a) The PIA (Programmable Interconnect Array) is deterministic - delay is independent of the path length. (b) Each LAB (Logic Array Block) contains a programmable AND array. (c) Interconnect timing within a LAB is also fixed. EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits , Michael John Sebastian Smith, Addison Wesley, 1997

Altera MAX 9000 Interconnect Architecture l Altera MAX 9000 devices use long row and column wires (Fast. Tracks) connected by switches Figure 7. 9 The Altera MAX 9000 interconnect scheme. (a) A 4 X 5 array of Logic Array Blocks (LABs), the same size as the EMP 9400 chip. (b) A simplified block diagram of the interconnect architecture showing the connection of the Fast. Track buses to a LAB. EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits , Michael John Sebastian Smith, Addison Wesley, 1997

Altera Flex l Altera Flex devices also use Fast. Tracks connected by switches, but the wiring is more dense (as are the logic modules) Figure 7. 10 The Altera FLEX interconnect scheme. (a) The row and column Fast. Track interconnect. (b) A simplified diagram of the interconnect architecture showing the connections between the Fast. Track buses and a LAB. EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits , Michael John Sebastian Smith, Addison Wesley, 1997