CSE 341 Verilog HDL An Introduction Hardware Specification

CSE 341 Verilog HDL An Introduction

Hardware Specification Languages l. Verilog FSimilar syntax to C FCommonly used in ÄIndustry (USA & Japan) l. VHDL FSimilar syntax to ADA FCommonly used in ÄGovernment Contract Work ÄAcademia ÄEurope

Structural vs. Behavioral l. Structural FShows primitive components and how they are connected FModules are defined as a collection of interconnected gates and other previously defined modules ÄModules are built up to make more complex modules FThe design describes the structure of the circuit l. Behavioral FShows functional steps of how the outputs are computed FAbstract description of how the circuit works FDoes not include any indication of structure (implementation) details FUseful early in design process ÄAllows designer to get a sense of circuit’s characteristics before embarking on design process ÄAfter functionality is well defined, structural design may follow FSynthesis Tools ÄGenerate implementation based on the behavioral specification

Overview l. System is described as a set of modules consisting of: FInterface ÄDeclares nets & registers which comprise the two (2) fundamental data types in Verilog ü Nets · Used to connect structures (eg. - gates) · Need to be driven ü Reg · Data storage element · Retain value until overwritten by another value · Don’t need to be driven FDescription ÄDefines structure

Modules l. Instantiating modules can help make code easier to write, modify, read, and debug l. Examples FCarry Lookahead Adder ÄPartial Full Adder ÄCarry Lookahead Unit FBarrel Shifter F 7 -Segment Display Decoder l. Basic Module Format

Modules l. Structure modulename(port list); parameters port declarations (input or output) wire declarations reg declarations submodule instantiations … text body … endmodule l. Instantiations Fmodulename instance_name(port list);

Datatypes l. Net FWire l. Register FReg FStatic Storage Element

Parameters l. Parameters FUsed to define constants in modules ÄExamples parameter and_delay=2, or_delay=1; and #and_delay (f, a, b);

Primitive Structural Modules l. Define the structure of the module FForm the module’s body l. Format Fgate #n (output, inputs) FNote: The integral delay (#n ) may be neglected ÄIf omitted, delay = 0 l. Gates Fand For Fnand Fnot Fxor

Identifiers l. Names given to hardware objects FWires (busses) FRegisters FMemories FModules l. Alphanumeric l. May Include: F_ F$ l. May NOT Start With: FNumber F$

Numbers l. Syntax FSized ÄSize’Format Number ÄSize ü Number of digits ÄFormat (Base) ü h (Hexadecimal) ü d (Decimal) Default ü o (Octal) ü b (Binary) ÄNumber ü Number specified FUnsized Ä’Format Number

Numbers l. Examples F 4’b 1011 F 8’hfe 902 a 30 F 2’d 37 ÄSame as 37 (default) F 4’h a 729 F‘d 62923 F 8’b 1101 zzzz F 16’h x

The Full Adder l. Consider a Full Adder

The Full Adder l. Basic Module module fulladder() ; wire w 1, w 2, w 3, w 4, s, cout; reg a, b, c; xor g 1(w 1, a, b), g 2(s, w 1, c); and g 3(w 2, c, b), g 4(w 3, c, a), g 5(w 4, a, b); or g 6(cout, w 2, w 3, w 4); --> Simulation <-endmodule

Simulation l. The simulation is an event-driven, timeordered depiction of the circuit’s behavior under the prescribed specifications. l. Structure initial begin Simulation end

Simulation l. Some Useful Simulation Commands F$monitor(“format”, variable list); ÄDisplays the specified entities when the values change ÄModelled after C’s printf ÄExtra commas add spaces in the output ÄFormat ü %b · bit ü %d · decimal ü %h · hexadecimal F$display (“format”, variable list); ÄSimilar to monitor, but displays variable list in the format specified whenever it is encountered

Simulation l. Some Useful Simulation Commands F$time ÄKeeps track of simulator’s time ÄUsed to maintain current time by simulator ÄThe simulation will display the time when an event occurs ÄReferenced by $time ÄSpecification of Units ü ‘timescale units / least significant digit to be printed ü Example · ‘timescale 10 ns / 100 ps · Units of 10 ns are used, printing out to no more precision than 100 ps

Simulation l. Some Useful Simulation Commands FIntegral Delay Ä#n ÄDelays action by n time units (as defined by the timescale) ü In other words… · n time units after the current time, the described event will take place ÄMay also be used for setting module & gate delays ü Example will follow

Simulation l. A bit in the simulation may take one of four values: F 1 (true) F 0 (false) FX (unknown) FZ (High Impedance)

The Full Adder l. Basic Module module fulladder() ; wire w 1, w 2, w 3, w 4, s, cout; reg a, b, c; xor g 1(w 1, a, b), g 2(s, w 1, c); and g 3(w 2, c, b), g 4(w 3, c, a), g 5(w 4, a, b); or g 6(cout, w 2, w 3, w 4); initial begin $monitor($time, , "a=%b, b=%b, c=%b, s=%b, cout=%b", a, b, c, s, cout); $display($time, , "a=%b, b=%b, c=%b, s=%b, cout=%b", a, b, c, s, cout); #10 a=0; b=0; c=0; #10 a=1; #10 b=1; #10 c=1; a=0; #10 a=1; #10 // Required for iverilog to show final values $display($time, , "a=%b, b=%b, c=%b, s=%b, cout=%b", a, b, c, s, cout); endmodule

Simulation l. Timescale FCompiler Directive ÄPreceded by ` ü Note, this is not an apostrophe F`timescale reference_time_unit / time_precision

The Full Adder l. Basic Module `timescale 1 ns/1 ns module fulladder() ; wire w 1, w 2, w 3, w 4, s, cout; reg a, b, c; xor g 1(w 1, a, b), g 2(s, w 1, c); and g 3(w 2, c, b), g 4(w 3, c, a), g 5(w 4, a, b); or g 6(cout, w 2, w 3, w 4); initial begin $monitor($time, , "a=%b, b=%b, c=%b, s=%b, cout=%b", a, b, c, s, cout); $display($time, , "a=%b, b=%b, c=%b, s=%b, cout=%b", a, b, c, s, cout); #10 a=0; b=0; c=0; #10 a=1; #10 b=1; #10 c=1; a=0; #10 a=1; #10 // Required for iverilog to show final values $display($time, , "a=%b, b=%b, c=%b, s=%b, cout=%b", a, b, c, s, cout); endmodule

Simulation l. Other Common Directives FDefine ÄDefines constants or macros ÄStructure ü `define name definition; ÄExample ü `define delay 1 FInclude ÄAllows for multiple source file use ü Not needed in Xilinx ÄStructure ü `include filename ÄExample ü `include multiplexors. v

Full Adder Functional Simulation l. Text Output # # # # 0 10 20 30 40 50 60 a=x, a=0, a=1, l. Waveform b=x, b=0, b=1, c=x, c=0, c=1, s=x, s=0, s=1, cout=x cout=0 cout=1

Full Adder Unit Delay Model l. Basic Module `timescale 1 ns/1 ns module fulladder() ; wire w 1, w 2, w 3, w 4, s, cout; reg a, b, c; xor #1 g 1(w 1, a, b), g 2(s, w 1, c); and #1 g 3(w 2, c, b), g 4(w 3, c, a), g 5(w 4, a, b); or #1 g 6(cout, w 2, w 3, w 4); initial begin $monitor($time, , "a=%b, b=%b, c=%b, s=%b, cout=%b", a, b, c, s, cout); $display($time, , "a=%b, b=%b, c=%b, s=%b, cout=%b", a, b, c, s, cout); #10 a=0; b=0; c=0; #10 a=1; #10 b=1; #10 c=1; a=0; #10 a=1; #10 // Required for iverilog to show final values $display($time, , "a=%b, b=%b, c=%b, s=%b, cout=%b", a, b, c, s, cout); endmodule

Full Adder Unit Delay Model l. Basic Module `timescale 1 ns/1 ns module fulladder() ; wire w 1, w 2, w 3, w 4, s, cout; reg a, b, c; xor #1 g 1(w 1, a, b), g 2(s, w 1, c); and #1 g 3(w 2, c, b), g 4(w 3, c, a), g 5(w 4, a, b); or #1 g 6(cout, w 2, w 3, w 4); initial begin $monitor($time, , "a=%b, b=%b, c=%b, s=%b, cout=%b", a, b, c, s, cout); $display($time, , "a=%b, b=%b, c=%b, s=%b, cout=%b", a, b, c, s, cout); #10 a=0; b=0; c=0; #10 a=1; #10 b=1; #10 c=1; a=0; #10 a=1; #10 // Required for iverilog to show final values $display($time, , "a=%b, b=%b, c=%b, s=%b, cout=%b", a, b, c, s, cout); endmodule

Full Adder Unit Delay Simulation l. Text Output # # # # 0 10 12 20 22 30 32 40 41 42 50 52 60 a=x, a=0, a=1, a=0, a=1, l. Waveform b=x, b=0, b=1, b=1, c=x, c=0, c=0, c=1, c=1, s=x, s=0, s=1, s=0, s=1, cout=x cout=0 cout=1 cout=1

Comments l. Single Line Comments FComment preceded by // FExample or #1 // OR gate with a g 6(cout, w 2, w 3, w 4); delay of one time unit l. Multiple Line Comments FComment encapsulated by /* and */ FExample and #1 g 1(e, a, b); /* In this circuit, the output of the AND gate is an input to the OR gate */ or #1 g 2(f, c, e);

Creating Ports l. Port names are known only inside the module l. Declarations FInput FOutput FBidirectional l. Full Adder Module

Creating Ports in the Full Adder `timescale 1 ns/1 ns module fulladder(a, b, c, s, cout); input a, b, c; output s, cout; xor #1 g 1(w 1, a, b), g 2(s, w 1, c); and #1 g 3(w 2, c, b), g 4(w 3, c, a), g 5(w 4, a, b); or #1 g 6(cout, w 2, w 3, w 4); endmodule

Creating Ports in the Full Adder `timescale 1 ns/1 ns module fulladder(a, b, c, s, cout); input a, b, c; output s, cout; xor #1 g 1(w 1, a, b), g 2(s, w 1, c); and #1 g 3(w 2, c, b), g 4(w 3, c, a), g 5(w 4, a, b); or #1 g 6(cout, w 2, w 3, w 4); endmodule

Instantiation l. Modules can be instantiated to complete a design l 4 -bit Ripple Carry Adder

Vectors l. Scalar FA single bit net or reg l. Vector FA multiple bit net or reg l. Advantage FVectors make for a more natural way of scaling up a design l. Example FConsider the 4 -bit adder ÄUsing scalars: ü A 3 A 2 A 1 A 0 + B 3 B 2 B 1 B 0 + Cin = Cout S 3 S 2 S 1 S 0 ÄUsing vectors: ü A + B + Cin = Cout, S ü A[3: 0] + B[3: 0] + Cin = Cout, S[3: 0]

Vectors l. Details Fwire and reg may be declared as multibit F[expression_1 : expression_2] FNote: ÄLeft expression is MSB, right is LSB ÄExpression must be constant, but may contain ü constants ü operators ü parameters

Vectors l. Concatenation FA bitvector can be created by concatenating scalar carriers and/or bitvectors FExample reg sum[3: 0] reg cout [cout, sum] l. Replication Fn{bitvector} FReplicates the bitvector n times. ÄExample ü 4{b’ 1001} results in 10011001

Creating the 4 -bit Adder `timescale 1 ns/1 ns module fulladder(a, b, c, s, cout); input a, b, c; output s, cout; xor #1 g 1(w 1, a, b), g 2(s, w 1, c); and #1 g 3(w 2, c, b), g 4(w 3, c, a), g 5(w 4, a, b); or #1 g 6(cout, w 2, w 3, w 4); endmodule four. Bit. Adder(x, y, s, cout, cin); input [3: 0] x, y; output [3: 0] s; input cin; output cout; wire c[3: 0]; fulladder endmodule f 0 f 1 f 2 f 3 (x[0], y[0], cin, s[0], c[0]); (x[1], y[1], c[0], s[1], c[1]); (x[2], y[2], c[1], s[2], c[2]); (x[3], y[3], c[2], s[3], cout);

Creating the 4 -bit Adder `timescale 1 ns/1 ns module fulladder(a, b, c, s, cout); input a, b, c; output s, cout; xor #1 g 1(w 1, a, b), g 2(s, w 1, c); and #1 g 3(w 2, c, b), g 4(w 3, c, a), g 5(w 4, a, b); or #1 g 6(cout, w 2, w 3, w 4); endmodule four. Bit. Adder(x, y, s, cout, cin); input [3: 0] x, y; output [3: 0] s; input cin; output cout; wire [3: 0] c; fulladder endmodule f 0 f 1 f 2 f 3 (x[0], y[0], cin, s[0], c[0]); (x[1], y[1], c[0], s[1], c[1]); (x[2], y[2], c[1], s[2], c[2]); (x[3], y[3], c[2], s[3], cout);

Creating a Testbench l. Provides for efficient testing of circuit l. Process FCreate a module dedicated for testing FInstantiate ÄTest Module ÄCircuit to be Tested FWire the modules together ÄNote that initial assignments in blocks must always be made to registers

Testbench for the 4 -bit Adder `timescale 1 ns/1 ns module testbench(); wire [3: 0] x, y, s; wire cin, cout; test. Adder test (x, y, s, cout, cin); four. Bit. Adder adder (x, y, s, cout, cin); endmodule test. Adder(a, b, s, cout, cin); input [3: 0] s; input cout; output [3: 0] a, b; output cin; reg [3: 0] a, b; reg cin; initial begin $monitor($time, , "a=%d, b=%d, c=%b, $display($time, , "a=%d, b=%d, c=%b, #20 a=2; b=3; cin=0; #20 a=1; b=7; cin=0; #20 // Required for iverilog $display($time, , "a=%d, b=%d, c=%b, s=%d, cout=%b", a, b, cin, s, cout); to show final values s=%d, cout=%b", a, b, cin, s, cout); endmodule // Don’t forget to include the four. Bit. Adder and fulladder modules

4 -bit Adder Unit Delay Simulation l. Text Output # # # # # 0 20 22 23 40 42 43 45 47 60 a= a= a= x, 2, 2, 2, 1, 1, 1, b= b= b= l. Waveform x, 3, 3, 3, 7, 7, 7, c=x, c=0, c=0, c=0, s= x, s= X, s= 5, s= 2, s=12, s= 0, s= 8, cout=x cout=0 cout=0

Icarus Verilog liverilog FAvailable on the CSE systems l. Using iverilog FEnter source code using any editor ÄSave using. v exention FCompile Äiverilog -t vvp filename. v -o out_filename ü Note that neglecting to specify the output filename (-o out_filename), iverilog will output to a. out. FView Results Ävpp out filename

Example l. Simulate the following circuit using Verilog HDL.

Example module eg_function(); reg a, b, c; wire f; ckt inst 1(f, a, b, c); initial begin $monitor($time, "a =%b, b=%b, c=%b, f=%b", a, b, c, f); $display($time, "a =%b, b=%b, c=%b, f=%b", a, b, c, f); #0 a=0; b=0; c=0; #10 a=1; b=1; c=1; #10 // Required for iverilog to show final values $display($time, "a =%b, b=%b, c=%b, f=%b", a, b, c, f); endmodule ckt(f, a, b, c); parameter delay=1; output f; input a, b, c; wire x, y; and #delay (x, a, b); or #delay (y, b, c); xor #delay (f, x, y); endmodule