Hardware Description Languages Verilog z Verilog y Structural

Hardware Description Languages: Verilog z Verilog y Structural Models y (Combinational) Behavioral Models y Syntax y Examples CS 150 - Fall 2005 - Lecture #4: Verilog - 1

Quick History of HDLs z ISP (circa 1977) - research project at CMU y Simulation, but no synthesis z Abel (circa 1983) - developed by Data-I/O y Targeted to programmable logic devices y Not good for much more than state machines z Verilog (circa 1985) - developed by Gateway (now Cadence) y Similar to Pascal and C y Delays is only interaction with simulator y Fairly efficient and easy to write y IEEE standard z VHDL (circa 1987) - Do. D sponsored standard y Similar to Ada (emphasis on re-use and maintainability) y Simulation semantics visible y Very general but verbose y IEEE standard CS 150 - Fall 2005 - Lecture #4: Verilog - 2

Design Methodology Structure and Function (Behavior) of a Design HDL Specification Simulation Synthesis Verification: Design Behave as Required? Functional: I/O Behavior Register-Level (Architectural) Logic-Level (Gates) Transistor-Level (Electrical) Timing: Waveform Behavior Generation: Map Specification to Implementation CS 150 - Fall 2005 - Lecture #4: Verilog - 3

Verilog/VHDL z The “standard” languages z Very similar y Many tools provide front-ends to both y Verilog is “simpler” x. Less syntax, fewer constructs y VHDL supports large, complex systems x. Better support for modularization x. More grungy details x“Hello world” is much bigger in VHDL CS 150 - Fall 2005 - Lecture #4: Verilog - 4

Verilog z Supports structural and behavioral descriptions z Structural y Explicit structure of the circuit y How a module is composed as an interconnection of more primitive modules/components y E. g. , each logic gate instantiated and connected to others z Behavioral y Program describes input/output behavior of circuit y Many structural implementations could have same behavior y E. g. , different implementations of one Boolean function CS 150 - Fall 2005 - Lecture #4: Verilog - 5

Verilog Introduction z the module describes a component in the circuit z Two ways to describe: y Structural Verilog x. List of components and how they are connected x. Just like schematics, but using text x. Hard to write, hard to decode x. Useful if you don’t have integrated design tools y Behavioral Verilog x. Describe what a component does, not how it does it x. Synthesized into a circuit that has this behavior CS 150 - Fall 2005 - Lecture #4: Verilog - 6

Structural Model y Composition of primitive gates to form more complex module y Note use of wire declaration! module xor_gate (out, a, b); By default, identifiers input a, b; are wires output out; wire abar, bbar, t 1, t 2; inverter and_gate or_gate inv. A (abar, a); inv. B (bbar, b); and 1 (t 1, a, bbar); and 2 (t 2, b, abar); or 1 (out, t 1, t 2); endmodule CS 150 - Fall 2005 - Lecture #4: Verilog - 7

Structural Model z Example of full-adder module full_addr (A, B, Cin, S, Cout); input A, B, Cin; output S, Cout; Behavior assign {Cout, S} = A + B + Cin; endmodule adder 4 (A, B, Cin, S, Cout); input [3: 0] A, B; input Cin; output [3: 0] S; output Cout; wire C 1, C 2, C 3; full_addr endmodule fa 0 fa 1 fa 2 fa 3 (A[0], (A[1], (A[2], (A[3], B[0], B[1], B[2], B[3], Cin, C 1, C 2, C 3, S[0], S[1], S[2], S[3], CS 150 - Fall 2005 - Lecture #4: Verilog - 8 Structural C 1); C 2); C 3); Cout);

Simple Behavioral Model z Combinational logic y Describe output as a function of inputs y Note use of assign keyword: continuous assignment module and_gate (out, in 1, in 2); input in 1, in 2; Output port of a primitive must output out; be first in the list of ports assign out = in 1 & in 2; Restriction does not apply to modules endmodule CS 150 - Fall 2005 - Lecture #4: Verilog - 9

Verilog Data Types and Values z Bits - value on a wire y 0, 1 y X - don’t care/don’t know y Z - undriven, tri-state z Vectors of bits y A[3: 0] - vector of 4 bits: A[3], A[2], A[1], A[0] y Treated as an unsigned integer value x e. g. , A < 0 ? ? y Concatenating bits/vectors into a vector x e. g. , sign extend x B[7: 0] = {A[3], A[3: 0]}; x B[7: 0] = {4{A[3]}, A[3: 0]}; y Style: Use a[7: 0] = b[7: 0] + c; Not: a = b + c; // need to look at declaration CS 150 - Fall 2005 - Lecture #4: Verilog - 10

Verilog Numbers z 14 - ordinary decimal number z -14 - 2’s complement representation z 12’b 0000_0110 - binary number with 12 bits (_ is ignored) z 12’h 046 - hexadecimal number with 12 bits z Verilog values are unsigned y e. g. , C[4: 0] = A[3: 0] + B[3: 0]; y if A = 0110 (6) and B = 1010(-6) C = 10000 not 00000 i. e. , B is zero-padded, not sign-extended CS 150 - Fall 2005 - Lecture #4: Verilog - 11

Verilog Operators CS 150 - Fall 2005 - Lecture #4: Verilog - 12

Verilog “Variables” z wire y Variable used simply to connect components together z reg y Variable that saves a value as part of a behavioral description y Usually corresponds to a wire in the circuit y Is NOT necessarily a register in the circuit z The Rule: y Declare a variable as a reg if it is the target of a concurrent (nonblocking) assignment statement x Don’t confuse reg assignments with the combinational continuous assign statement! x Reg should only be used with always blocks (sequential logic, to be presented …) x Confusing isn’t it? CS 150 - Fall 2005 - Lecture #4: Verilog - 13

Verilog Module z Corresponds to a circuit component y “Parameter list” is the list of external connections, aka “ports” y Ports are declared “input”, “output” or “inout” xinout ports used on tri-state buses y Port declarations imply that the variables are wires module name ports module full_addr (A, B, Cin, S, Cout); input A, B, Cin; output S, Cout; assign {Cout, S} = A + B + Cin; endmodule CS 150 - Fall 2005 - Lecture #4: Verilog - 14 inputs/outputs

Verilog Continuous Assignment z Assignment is continuously evaluated z assign corresponds to a connection or a simple component with the described function z Target is NEVER a reg variable use of Boolean operators (~ for bit-wise, ! for logical negation) assign A = X | (Y & ~Z); bits can take on four values (0, 1, X, Z) assign B[3: 0] = 4'b 01 XX; assign C[15: 0] = 12'h 00 ff; variables can be n-bits wide (MSB: LSB) assign #3 {Cout, S[3: 0]} = A[3: 0] + B[3: 0] + Cin; use of arithmetic operator multiple assignment (concatenation) delay of performing computation, only used by simulator, not synthesis CS 150 - Fall 2005 - Lecture #4: Verilog - 15

Comparator Example module Compare 1 (A, B, Equal, Alarger, Blarger); input A, B; output Equal, Alarger, Blarger; assign Equal = (A & B) | (~A & ~B); assign Alarger = (A & ~B); assign Blarger = (~A & B); endmodule CS 150 - Fall 2005 - Lecture #4: Verilog - 16

Comparator Example // Make a 4 -bit comparator from 4 x 1 -bit comparators module Compare 4(A 4, B 4, Equal, Alarger, Blarger); input [3: 0] A 4, B 4; output Equal, Alarger, Blarger; wire e 0, e 1, e 2, e 3, Al 0, Al 1, Al 2, Al 3, B 10, Bl 1, Bl 2, Bl 3; Compare 1 cp 0(A 4[0], cp 1(A 4[1], cp 2(A 4[2], cp 3(A 4[3], B 4[0], B 4[1], B 4[2], B 4[3], e 0, e 1, e 2, e 3, assign Equal = (e 0 & e 1 & e 2 assign Alarger = (Al 3 | (Al 2 (Al 1 & e 3 & (Al 0 & e 3 & assign Blarger = (~Alarger & endmodule Al 0, Al 1, Al 2, Al 3, Bl 0); Bl 1); Bl 2); Bl 3); & e 3); & e 3) | e 2 & e 1)); ~Equal); CS 150 - Fall 2005 - Lecture #4: Verilog - 17

Announcements z Card Key Access to 125 Cory y EECS Keys/Cardkeys, Copy Cards Assistant y Loretta Lutcher y 253 Cory, 642 -1527, loret@eecs x Issues keys and electronic cardkeys for Cory and Soda Halls. Handles cardkey problems z From the Reader on Quiz #1: y Common mistakes: x Inverted 1’s and the 0’s (PM vs. Sm notation) x No overlapping circles, or not the largest circle possible for K- maps for simplest So. P result (minimum cover, what constitutes adjacency) x Many mixed up the order on the K-map (some people started with 1, a lot were confused) (e. g. , Gray code order: 0 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10) CS 150 - Fall 2005 - Lecture #4: Verilog - 18

Simple Behavioral Model: the always block z always block y Always waiting for a change to a trigger signal y Then executes the body module and_gate (out, in 1, in 2); input in 1, in 2; output out; reg out; always @(in 1 or in 2) begin out = in 1 & in 2; endmodule Not a real register!! A Verilog register Needed because of assignment in always block Specifies when block is executed I. e. , triggered by which signals CS 150 - Fall 2005 - Lecture #4: Verilog - 19

always Block z Procedure that describes the function of a circuit y Can contain many statements including if, for, while, case y Statements in the always block are executed sequentially x(Continuous assignments <= are executed in parallel) y Entire block is executed at once y Final result describes the function of the circuit for current set of inputs xintermediate assignments don’t matter, only the final result z begin/end used to group statements CS 150 - Fall 2005 - Lecture #4: Verilog - 20

“Complete” Assignments z If an always block executes, and a variable is not assigned y Variable keeps its old value (think implicit state!) y NOT combinational logic latch is inserted (implied memory) This is usually not what you want: dangerous for the novice! z Any variable assigned in an always block should be assigned for any (and every!) execution of the block CS 150 - Fall 2005 - Lecture #4: Verilog - 21

Incomplete Triggers z Leaving out an input trigger usually results in a sequential circuit z Example: Output of this “and” gate depends on the input history module and_gate (out, in 1, in 2); input in 1, in 2; output out; reg out; always @(in 1) begin out = in 1 & in 2; endmodule CS 150 - Fall 2005 - Lecture #4: Verilog - 22

Verilog if z Same as C if statement // Simple 4: 1 mux module mux 4 (sel, A, B, C, D, Y); input [1: 0] sel; // 2 -bit control signal input A, B, C, D; output Y; reg Y; // target of assignment always @(sel or A or B or C or D) if (sel == 2’b 00) Y = A; else if (sel == 2’b 01) Y = B; else if (sel == 2’b 10) Y = C; else if (sel == 2’b 11) Y = D; endmodule CS 150 - Fall 2005 - Lecture #4: Verilog - 23

Verilog if z Another way // Simple 4: 1 mux module mux 4 (sel, A, B, C, D, Y); input [1: 0] sel; // 2 -bit control signal input A, B, C, D; output Y; reg Y; // target of assignment always @(sel or A or if (sel[0] == 0) if (sel[1] == 0) else endmodule B or C or D) Y = A; Y = B; Y = C; Y = D; CS 150 - Fall 2005 - Lecture #4: Verilog - 24

Verilog case z Sequential execution of cases y Only first case that matches is executed (no break) y Default case can be used // Simple 4 -1 mux module mux 4 (sel, A, B, C, D, Y); input [1: 0] sel; // 2 -bit control signal input A, B, C, D; output Y; reg Y; // target of assignment always @(sel case (sel) 2’b 00: Y 2’b 01: Y 2’b 10: Y 2’b 11: Y endcase endmodule or A or B or C or D) = = A; B; C; D; CS 150 - Fall 2005 - Lecture #4: Verilog - 25 Conditions tested in top to bottom order

Verilog case z Without the default case, this example would create a latch for Y z Assigning X to a variable means synthesis is free to assign any value // Simple binary encoder (input is 1 -hot) module encode (A, Y); input [7: 0] A; // 8 -bit input vector output [2: 0] Y; // 3 -bit encoded output reg [2: 0] Y; // target of assignment always @(A) case (A) 8’b 00000001: 8’b 00000010: 8’b 00000100: 8’b 00001000: 8’b 00010000: 8’b 00100000: 8’b 01000000: 8’b 10000000: default: endcase endmodule Y Y Y Y Y = = = = = 0; 1; 2; 3; 4; 5; 6; 7; 3’b. X; // Don’t care when input is not 1 -hot CS 150 - Fall 2005 - Lecture #4: Verilog - 26

Verilog case (cont) z Cases are executed sequentially y Following implements a priority encoder // Priority encoder module encode (A, Y); input [7: 0] A; output [2: 0] Y; reg [2: 0] Y; always @(A) case (1’b 1) A[0]: Y A[1]: Y A[2]: Y A[3]: Y A[4]: Y A[5]: Y A[6]: Y A[7]: Y default: Y endcase endmodule = = = = = 0; 1; 2; 3; 4; 5; 6; 7; 3’b. X; // 8 -bit input vector // 3 -bit encoded output // target of assignment // Don’t care when input is all 0’s CS 150 - Fall 2005 - Lecture #4: Verilog - 27

Parallel Case z A priority encoder is more expensive than a simple encoder y If we know the input is 1 -hot, we can tell the synthesis tools y “parallel-case” pragma says the order of cases does not matter // simple encoder module encode (A, Y); input [7: 0] A; output [2: 0] Y; reg [2: 0] Y; always @(A) case (1’b 1) A[0]: Y A[1]: Y A[2]: Y A[3]: Y A[4]: Y A[5]: Y A[6]: Y A[7]: Y default: Y endcase endmodule // 8 -bit input vector // 3 -bit encoded output // target of assignment // synthesis parallel-case = = = = = 0; 1; 2; 3; 4; 5; 6; 7; 3’b. X; // Don’t care when input is all 0’s CS 150 - Fall 2005 - Lecture #4: Verilog - 28

Verilog casex z Like case, but cases can include ‘X’ y X bits not used when evaluating the cases y In other words, you don’t care about those bits! CS 150 - Fall 2005 - Lecture #4: Verilog - 29

casex Example // Priority encoder module encode (A, valid, Y); input [7: 0] A; output [2: 0] Y; output valid; reg [2: 0] Y; reg valid; always @(A) begin valid = 1; casex (A) 8’b. XXXXXXX 1: Y = 8’b. XXXXXX 10: Y = 8’b. XXXXX 100: Y = 8’b. XXXX 1000: Y = 8’b. XXX 10000: Y = 8’b. XX 100000: Y = 8’b. X 1000000: Y = 8’b 10000000: Y = default: begin valid = 0; Y = 3’b. X; // endcase endmodule // // 8 -bit input vector 3 -bit encoded output Asserted when an input is not all 0’s target of assignment 0; 1; 2; 3; 4; 5; 6; 7; Don’t care when input is all 0’s CS 150 - Fall 2005 - Lecture #4: Verilog - 30