COMP 541 Arithmetic Circuits Montek Singh Mar 20

COMP 541 Arithmetic Circuits Montek Singh Mar 20, 2007 1

Topics ã Adder circuits ã How to subtract l Why complemented representation works out so well ã Overflow 2

Iterative Circuit ã Like a hierachy, except functional blocks per bit 3

Adders ã Great example of this type of design ã Design 1 -bit circuit, then expand ã Let’s look at l Half adder – 2 -bit adder, no carry in Ø Inputs are bits to be added Ø Outputs: result and possible carry l Full adder – includes carry in, really a 3 -bit adder 4

Half Adder ãS=X Y ã C = XY 5

Full Adder ã Three inputs. Third is Cin ã Two outputs: sum and carry 6

Two Half Adders (and an OR) 7

Ripple-Carry Adder ã Straightforward – connect full adders ã Carry-out to carry-in chain l C 0 in case this is part of larger chain, or just ‘ 0’ 8

Hierarchical 4 -Bit Adder ã We can easily use hierarchy here ã Design half adder ã Use in full adder ã Use full adder in 4 -bit adder ã Verilog code in textbook 9

Behavioral Verilog // 4 -bit Adder: Behavioral Verilog module adder_4_b_v(A, B, C 0, S, C 4); input[3: 0] A, B; input C 0; output[3: 0] S; Addition (unsigned) output C 4; assign {C 4, S} = A + B + C 0; endmodule Concatenation operation 10

What’s Problem with Design? ã Delay l Approx how much? ã Imagine a 64 -bit adder l Look at carry chain 11

Carry Lookahead Adder ã Note that add itself just 2 level ã Idea is to separate carry from adder function l Then make carry approx 2 -level all way across larger adder 12

Four-bit Ripple Carry Reference Adder function separated from carry Notice adder has A, B, C in and S out, as well as G, P out. 13

Propagate ã The P signal is called propagate ãP=A B ã Means to propagate incoming carry 14

What Does This Mean? ã No Carry Here ã So the propagate signal indicates that condition of incoming should pass on 15

Generate ã The G is generate ã It’s G = AB, so new carry created ã So it’s ORed with incoming carry 16

Said Differently ã If A B and there’s incoming carry, carry will be propagated l And S will be 0, of course ã If AB, then will create carry l Incoming will determine whether S is 0 or 1 17

Ripple Carry Delay: 8 Gates 18

Turn Into Two Gate Delays ã Design changed from deep (in delay) to wide 19

C 1 Just Like Ripple Carry 20

C 2 Circuit Two Levels G from before and P to pass on This checks two propagates and a carry in 21

C 3 Circuit Two Levels Generate from level 0 and two propagates G from before and P to pass on This checks three propagates and a carry in 22

What Happens as Scale Up? ã Can I realistically make 64 -bit adder like this? ã Have to AND 63 propagates and Cin! ã Compromise l Hierarchical design l More levels of gates 23

Making 4 -Bit Adder Module ã Create propagate and generate signals for whole module 24

Group Propagate ã Make propagate of whole 4 -bit block ã P 0 -3 = P 3 P 2 P 1 P 0 25

Group Generate ã Does G created upstream pass on because of string of Ps (also G 3)? ã Indicates carry generated in block 26

Hierarchical Carry A A B 4 -bit adder S G P B 4 -bit adder Cin S G P Cin C 4 C 8 Look Ahead C 0 Left lookahead block is exercise for you 27

Practical Matters ã FPGAs like ours have limited inputs per block ã Instead they have special circuits to make adders ã So don’t expect to see same results as theory would suggest 28

On to Subtraction ã First, look at unsigned numbers l Motivates why we typically use complemented representation ã Then look at 2 s complement ã Imagine a subtractor circuit (next) 29

One-bit Subtractor ã Inputs: Borrow in, l minuend and subtrahend Review: subtrahend is subtracted from minuend ã Outputs: Difference, borrow out ã Could use like adder ã One per bit M Bout S 1 -bit sub Bin D 30

Example Borrow 1 0 If no borrow, then result is non-negative (minuend >= subtrahend). 0 Minuend 0 1 1 Subtrahend 1 1 0 Difference 1 0 1 Correct Diff - 0 1 1 Since there is borrow, result must be negative. The magnitude must be corrected. Next slide. 31

Correcting Result ã What, mathematically, does it mean to borrow? ã If borrowing at digit i-1 you are adding 2 i ã Next Slide 32

Correcting Result 2 ã If M is minuend and N subtrahend of numbers length n, difference was 2 n + M – N ã What we want is magnitude of N-M (with minus sign in front) ã Can get by subtracting previous result from 2 n N - M = 2 n – (M – N + 2 n) This is called 2’s complement 33

Put Another Way ã This is equivalent to how we do subtraction in our heads l Decide which is greater l Swap if necessary l Subtract ã Could build a circuit this way… l Or just look at borrow bit 34

Algorithm Subtract N from M 2. If no borrow, then M N and result is OK 3. Otherwise, N > M so result must be subtracted from 2 n (and minus sign prepended) 1. 35

Pretty Expensive Hardware! 36

That Complex Design not Used ã That’s why people use for numbers complemented interpretation l 2’s complement l 1’s complement 37

1’s Complement ã Given: binary number N with n digits ã 1’s complement defined as (2 n – 1) - N 2 n - 1 1 1 1 -N 1 0 1 1 0 0 1 1’s Compl. 0 1 0 0 1 1 0 38

2’s Complement ã Given: binary number N with n digits ã 2’s complement defined as 2 n – N for N 0 0 for N = 0 l Exception is so result will always have n bits ã 2’s complement is just a 1 added to 1’s complement 39

Important Property ã Complement of a complement generates original number ã NOTE: We haven’t talked about negative numbers yet. Still looking at unsigned ã Let’s look at new design for subtractor 40

New Algorithm for M-N Add 2’s complement of N to M 1. l This is M + (2 n – N) = M – N + 2 n If M N, will generate carry (why? ) 2. • • Discard carry Result is positive M - N If M < N, no end carry (why? ) 3. • • Take 2’s complement of result Place minus sign in front 41

Example ã X = 101_0100 minus Y = 100_0011 X 1 0 1 0 0 + 2’s comp Y 0 1 1 0 1 0 0 0 1 Sum 1 42

Example 2 ã Y = 100_0011 minus X = 101_0100 Y 1 0 0 1 1 + 2’s comp X 0 1 1 0 0 Sum 1 1 0 1 1 ã No end carry ã Answer: - (2’s complement of Sum) ã - 0010001 43

Adder-Subtractor ã Need only adder and complementer for input to subtract ã Need selective complementer to make negative output back from 2’s complement l Or go through adder again. See next slide 44

Design of Adder/Subtractor S low for add, high for subtract Inverts each bit of B if S is 1 Adds 1 to make 2’s complement ã Output is 2’s complement if B > A 45

Signed Arithmetic ã Review characteristics of signed representations ã Signed magnitude l Left bit is sign, 0 positive, 1 negative l Other bits are number ã 2’s complement ã 1’s complement 46

Observations ã 1’s C and Signed Mag have two zeros ã 2’s C has more negative than positive ã All negative numbers have 1 in high-order 47

Advantages/Disadvantages ã Signed magnitude has problem that we need to correct after subtraction ã One’s complement has a positive and negative zero ã Two’s complement is most popular l Arithmetic operations easy 48

Conclusion: 2’s Complement ã Addition easy on any combination of positive and negative numbers ã To subtract l Take 2’s complement of subtrahend l Add l This performs A + ( -B), same as A – B 49

Overflow ã Two cases of overflow for addition of signed numbers l Two large positive numbers overflow into sign bit Ø Not enough room for result l Two large negative numbers added Ø Same – not enough bits ã Carry out can be OK 50

Examples ã 4 -bit signed numbers ã 7+7 ã 7– 7 l Generates carry but result OK ã -7 -7 ã 4+4 l Generates no Cout, but overflowed 51

Overflow Detection ã Condition is that either Cn-1 or Cn is high, but not both 52