Combinational Logic Design Combinational Circuits Design Topics Analysis
Combinational Logic Design • • • Combinational Circuits Design Topics Analysis Procedure Design Procedure Common Building Blocks Hardware Design Languages Read MK 87 -124, 141 -161, 201 -229
4 Bit ALU Design Elements Negate A B 4 Bit Adder Negate 4 Bit Adder D S if S=0 then D=B-A if S=1 then D=A-B if S=2 then D=A+B if S=3 then D=-A 3. 2 - Jon Turner - 1/29/2022 Quad 4: 1 Multiplexor
Combinational Circuits A Combinational Circuit A Non-combinational Circuit B B n In combinational circuits, there is no way for a signal to flow from a gate output to one of its inputs. » so, outputs depend only on current input values (not past) » non-combinational circuits use feedback to implement storage n Combinational circuits are essential building blocks. n Each output of a combinational circuit is a function of input values. » each output can be specified by a truth table or Boolean exp. » analysis: circuit specification » synthesis: specification circuit 3. 3 - Jon Turner - 1/29/2022 the
Hierarchical Design n Complex systems are designed by assembling simpler parts in a systematic and (usually) hierarchical way. » complex function at top of hierarchy, simple gates at bottom » design process can be top-down or bottom-up n Key concept is composition of simpler circuit blocks to produce more complex blocks. top level spec X 0 X 1 X 2 9 input X 3 odd Z 0 X 4 X 5 X 6 function X 7 X 8 X 0 3 input Z 0 X 1 X 2 odd Z 0=odd(X 0, …, X 8)=odd(X 0, X 1, X 2), odd(X 3, X 4, X 5), odd(X 6, X 7, X 8)) 3. 4 - Jon Turner - 1/29/2022 odd(X 0, X 1, X 2) =odd(X 0, odd(X 1, X 2)) odd(X 0, X 1)= nand(X 0, X 1)), nand(X 1, nand(X 0, X 1)))
Design Concepts n Hierarchical design is essential for managing complexity & allows us to understand larger circuits. n Design re-use is a key tool for reducing design effort. » apply common building blocks (functional blocks) to construct larger systems » large designs may contain many instances of a given block » generic design elements implement common functions but may differ based on parameter values – e. g. an odd function block, with number of inputs as a parameter n Top-down design, goes from high level specification to simpler components using iterative refinement. n In bottom-up design, we identify & construct common elements that can be re-used multiple times. 3. 5 - Jon Turner - 1/29/2022
Analyzing Combinational Circuits n Purpose of analysis is to determine what a circuit does. n Procedure 1. verify that circuit is combinational 2. label all inputs, outputs and internal nets 3. write logic equations for internal nets in terms of inputs 4. write logic equations for outputs in terms of inputs and simplify T 1=B C T 2=A B A T 3 T =A+B C D 3 T 1 F 1 T 2 T 4 F 2 3. 6 - Jon Turner - 1/29/2022 1 T 4=T 2 D=A B D F 1=T 3+T 4 =A+B C+B D +BD F 2=T 2+D=A B+D
Derivation of Truth Tables n Can derive truth tables directly from circuit. n Procedure 1. For n input circuit, truth table has 2 n rows, one for each binary number from 0 to 2 n-1. 2. Label internal nets and place columns in truth table for ABCD T 1 T 2 T 3 T 4 internal nets and outputs. 0000 0 0 3. Fill in columns for internal nets 0001 0 0 0 1 0010 1 0 and outputs. 0011 1 0100 0 1 A T 3 B C D T 1 F 1 T 2 T 4 F 2 3. 7 - Jon Turner - 1/29/2022 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 0 0 1 1 1 0 0 0 1 1 1 1 0 1 0 1 0 1 F 2 0 1 1 1 1 0 1 0 1
Designing Combinational Circuits n Procedure 1. Determine number of inputs and outputs and assign a symbol to each. 2. Derive truth table for each output. 3. Obtain Boolean expressions for each output. 4. Create an appropriate logic diagram. 5. Verify correctness by analysis and/or simulation. » Example: design circuit with 3 inputs, 1 output; the output should be 1 when the binary value of the inputs is <3. XYZ 000 001 010 011 100 101 110 111 F 1 1 1 0 0 0 3. 8 - Jon Turner - 1/29/2022 YZ 00 01 11 10 X 0 1 1 0 0 F =X Y +X Z X Y Z F
BCD to Excess 3 Code Converter n Excess-3 code for a decimal digit is the binary value for the decimal number plus 3. input output CD A B C D 3. 9 - Jon Turner - 1/29/2022 W X Y Z ABCD WXYZ 0000 0011 0001 0100 0010 0101 0011 0110 0100 0111 0101 1000 0110 1001 0111 1010 1000 1011 1001 1100 CD 00 01 11 10 AB 00 0 1 1 1 0 0 0 11 x x 10 0 1 x x AB 00 01 11 10 0 0 x 1 0 1 x x W=A+BC +BD CD 00 01 11 10 AB 00 1 0 01 1 0 11 x x 10 1 0 x x X=B C +B D +BC D Y=CD +C D
Decoders n. A binary-to-unary decoder converts a binary input value with n bits to one of 2 n possible output values. 3 8 Decoder A 0 A 1 A 2 000 001 010 011 100 101 110 111 D 7. . D 0 000000010 000001000 000100000 010000000 D 1 D 2 D 3 D 4 D 5 A 0 A 1 E 2 4 Decoder Alternative Implementation 3. 10 - Jon Turner - 1/29/2022 D 4 D 5 D 6 D 7 A 0 A 1 E 2 4 Decoder A 0 A 1 A 2 A 1 A 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 6 D 7 A 2 A 1 A 0
Decoder Schematic & Simulation 3. 11 - Jon Turner - 1/29/2022
Encoders n. A unary-to-binary encoder converts one of 2 n input values to an encoded binary value. D 3 D 2 D 1 D 0 A 1 A 0 0001 00 0010 01 0100 10 1000 11 A 1=D 2+D 3 A 0=D 1+D 3 n. A priority encoder converts the first of 2 n input values that are 1 to the corresponding encoded binary value. D 3 D 2 D 1 D 0 A 1 A 0 V 0000 xx 0 0001 001 x 011 01 xx 101 1 xxx 111 3. 12 - Jon Turner - 1/29/2022 A 1=D 3+D 2 A 0=D 3+D 2 D 1 V= D 3+D 2+D 1+D 0 -- valid output
Multiplexers n. A multiplexer (a. k. a. data selector) has n control inputs, 2 n data inputs & a single data output » control input value connects one data input to output » circuit similar to decoder » optional enable input allows construction of larger muxes –implement with AND at output D 0 D 1 D 2 D 3 Y D 4 D 5 D 6 D 7 » alternative implementation uses transmission gates S 2 3. 13 - Jon Turner - 1/29/2022 S 1 S 0
Demultiplexers n. A demultiplexer has n control inputs, 2 n data outputs & a single data input » control input value connects data input to one of the outputs n Mux & demux can be used to transmit several low speed signals on a single wire. D 0 D 1 D 2 D 3 X D 4 D 5 D 6 D 0 D 1 D 2 D 3 S 1 S 0 D 7 S 1 S 0 S 2 3. 14 - Jon Turner - 1/29/2022 S 1 S 0
Choosing the Best Circuit n Often there are many alternative circuits we can use. » trade-off between circuit cost and performance n The complexity of a circuit is the number of elementary components needed to implement it. » often, we count simple gates (or “gate equivalents”) » example – 8 bit decoder on page 3. 10 requires 19 simple gates – an n bit decoder using the same design requires n(log 2 n -1) + log 2 n simple gates n The worst-case delay of a circuit is the maximum time required for an input signal change to affect an output. » estimate by looking for longest input-to-output path (most simple gates) and counting one “unit” per gate in path » can estimate more precisely if gate delays are given 3. 15 - Jon Turner - 1/29/2022
Increment Circuit and Half Adders A 0 increment circuit with n A 1 inputs and n+1 outputs computes A 2 A 3 binary value that is one larger than its input. n It can be implemented using n linked halfadder circuits. S 0 S 1 S 2 S 3 S 4 increment n An » to obtain a selectable incrementer replace the constant 1 input with a control input » time for increment grows Cin with number of bits Ai S 0 A 1 S 1 A 2 S 2 A 3 Si Cout 3. 16 - Jon Turner - 1/29/2022 A 0 1 S 4
Addition Circuit and Full Adders n Addition 0 A 0 B 0 A 1 B 1 A 2 B 2 A 3 B 3 S 0 A 0 B 0 FA S 0 S 2 AB 1 FA S 1 A 2 S 4 B 2 FA S 2 A 3 B 3 FA S 3 S 1 add circuit with 2 n inputs & n+1 outputs computes the binary sum of two input values. n It can be implemented using n linked full-adder circuits. n A full-adder can be built from 2 half-adders. 1 S 3 Cin A B S Cin n This A B Cout FA S=A B Cin Cout=AB+BC +ACin addition circuit is called a ripple carry adder » takes time proportional to n to add two n bit numbers 3. 17 - Jon Turner - 1/29/2022 S 4
Simulation of Adder Circuit Functional Simulation (no gate delays) Timing Simulation (post place & route) 3. 18 - Jon Turner - 1/29/2022
Binary Multiplication n Binary multiplication is done much like decimal multiplication. 1101 1010 0000 1101 10000010 Y 1 . X 3. X 2. X 1 X 0 Addend multiplicand multiplier partial products Y 0. X 3. X 2. X 1 X 0 Augend Adder C Y 2 . X 3. X 2. X 1 X 0 Addend 1 bit multipliers (AND gates) and addition circuits. n Can speedup by rearranging so additions occur in parallel. Augend Adder product n Requires Sum C Y 3 . X 3. X 2. X 1 Sum X 0 Addend Augend Adder C Sum P 7 P 6 P 5 P 4 P 3 P 2 P 1 P 0 3. 19 - Jon Turner - 1/29/2022
Incrementer with Carry Look-ahead n Can speed up incrementer using carry lookahead. n Compute carry out of each position directly from inputs. inc X 0 S 0 X 1 S 1 X 2 S 2 X 3 S 3 » redundant AND operations, but faster n Speed comparison » assumptions: 2 input gate has 1 ns delay, 3 or 4 input gate has 2 ns delay, 5 to 8 input gate has 3 ns delay, . . . » 64 bit ripple carry incrementer needs 64 ns in worst-case » 64 bit carry-lookahead incrementer needs 7 ns in worst-case n So, what’s the catch? » carry lookahead uses 2000 “simple gate equivalents” » inputs must drive many gates 3. 20 - Jon Turner - 1/29/2022 S 4
More Scalable Carry Lookahead EN=c 0 x 0 c 1= EN x 0 x 1 x 1 x 2 EN x 0 x 1 x 2 x 2 x 3 x 0 x 1 x 2 x 3 x 1 x 2 x 3 x 4 x 5 x 4 x 5 x 2 x 3 x 4 x 5 x 5 x 6 x 3 x 4 x 5 x 6 x 6 x 7 x 4 x 5 x 6 x 7 x 6 x 7 n 64 x 1 x 2 x 3 x 4 c 2= EN x 0 x 1 c 3= EN x 0 x 1 x 2 c 4= EN x 0 x 1 x 2 x 3 c 5= EN x 0 x 1 x 2 x 3 x 4 c 6= EN x 0 x 1 x 2 x 3 x 4 x 5 c 7= EN x 0 x 1 x 2 x 3 x 4 x 5 x 6 c 8= EN x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 7 bit version has 7 ns delay, about 380 gates for carry, fanout=6. 3. 21 - Jon Turner - 1/29/2022
Carry Lookahead Adder n Ripple carry adder is too slow for fast addition of large values (typical computer uses 32 or 64 bit arithmetic). n To get a faster circuit, replace long carry chain with a “shorter” circuit. First separate carry logic in FA. X Y S partial full adder Cin Cout generate propagate » So high order carries can be generated with low delay, at the cost of more gates. 3. 22 - Jon Turner - 1/29/2022 Let Gi be generate signal for bit i, Pi be propagate signal and Ci be carry into bit i. C 2=G 1+C 1 P 1=G 1+G 0 P 1+C 0 P 0 P 1 and C 3=G 2+C 2 P 2 =G 2+(G 1+G 0 P 1+C 0 P 0 P 1)P 2 =G 2+G 1 P 2+G 0 P 1 P 2+C 0 P 0 P 1 P 2 and so forth.
Simulation of Carry Lookahead Adder C 0 C 1 C 2 C 3 Functional Simulation (0 gate delays) C 4 Unit Delay Simulation (1 ns delay per gate) 3. 23 - Jon Turner - 1/29/2022
More Scalable Lookahead Adder A more scalable lookahead adder can be obtained by writing the logic equations differently. n Let G(i, j) be true if a carry is generated from within the bits i -j+1 up to i: G(i, j)=Gi + Gi-1 Pi + + Gi-j+1 Pi-j+2 Pi n Let P(i, j)=Pi Pi-j+1. n Now, we can also write, G(i, 1)=Gi P(i, 1)=Pi G(i, 2)=G(i, 1)+G(i-1, 1)P(i, 1) P(i, 2)=P(i, 1)P(i-1, 1) G(i, 4)=G(i, 2)+G(i-2, 2)P(i, 2) P(i, 4)=P(i, 2)P(i-2, 2) G(i, 8)=G(i, 4)+G(i-4, 4)P(i, 4) P(i, 8)=P(i, 4)P(i-4, 4) n These equations lead directly to the design on the following page. n 3. 24 - Jon Turner - 1/29/2022
Lookahead Adder Schematic Up to 2+2 log 2 n gate delays. About 3 n+3 nlog 2 n gates. P(i-j, j) Partial full adder P(i, j) P(i, 2 j) G(i-j, j) G(i, j) 3. 25 - Jon Turner - 1/29/2022 G(i, 2 j)
Linear Circuit Pattern n Ripple-carry increment and addition circuits are examples of a common linear circuit pattern. » copies of a common “block” with one or more signals between adjacent blocks. . . n Other circuits with similar pattern. » 2 s-complementer, maximum, comparison, count-ones, . . . n n Propagation delay for such circuits typically grows in proportion to number of blocks. Look-ahead versions can have propagation delays that grow with logarithm of number of blocks. 3. 26 - Jon Turner - 1/29/2022
Modular and Signed Arithmetic 01 10 10 10 000 00 1 10 6 11 3 00 4 0100 50 101 10 01 1 011 1000 0011+0110 =1001 0000 00 1 10 1111+0011=0010 11 10 -1 0 1 110 2 -2 1 -7 -8 7 01 10 10 10 -3 1100 -4 1 -5 1 0 -6 1 6 11 3 00 4 0100 50 101 10 01 1 011 1000 3. 27 - Jon Turner - 1/29/2022 9 8 7 1 certain bit patterns with negative values yields signed arithmetic. n Negate a given value by flipping all bits and adding 1. 13 1100 12 11 1 1 10 10 111 n Associating 11 10 15 0 1 110 2 1 14 1 » to add A+B, start at position for A and then count clockwise B positions » standard addition algorithm does exactly this. 111 overflows are discarded, binary adders actually implement modulo arithmetic in which values wrap around circularly. 1111+0011=0010 n If
2’s Complement and Subtraction n In 2’s complement arithmetic with n bits: » the first bit represents the sign (0 for positive, 1 for negative) » for positive numbers, the remaining n-1 bits give the magnitude in standard binary notation » to convert a positive number to corresponding negative number, flip all bits and add 1 (0011 1100+1=1101) » to convert a negative number to corresponding positive number, flip all bits and add 1 (1101 0010+1=0011) n To subtract, take complement and add. » 410 -710 = 0100 -0111 = 0100+(-0111) = 0100+1001 = 1101 = -310 n 2’s complement is most popular method for representing negative numbers. » requires no special subtraction circuit, just addition and complement 3. 28 - Jon Turner - 1/29/2022
Adder-Subtracter n When sub=0, result is A+B. n When sub=1 » bit flipper complements all bits of B » adder sums and adds 1 A-B = A + (-B) = A + (not(B) + 1) = A + not(B) + 1 n Takes just slightly more time than “plain” adder. 3. 29 - Jon Turner - 1/29/2022 A 3 A 2 A 1 A 0 B 3 B 2 B 1 B 0 bit flipper sub Cout Adder R 3 R 2 R 1 R 0 Cin
11 110 10 1 1’s complement arithmetic, negate a value by flipping bits (do not also add 1). 111 n In 2 -6 -7 7 10 1 10 0 01 » gives two different representations for zero » when adding two values, if carry out of most significant digit, increment to obtain final sum » comparable to 2’s complement but not quite as simple -0 0 1 6 11 3 00 4 0100 50 101 10 01 1 011 1000 1 -1 -2 1100 -3 1 -4 1 0 -5 1 0000 00 1 10 Alternative Negative Number Formats 3. 30 - Jon Turner - 1/29/2022 110 10 -7 0 1 -1 -0 7 01 10 10 10 1 -6 -5 1100 -4 1 -3 1 0 -2 1 2 6 11 3 00 4 0100 50 101 10 01 1 011 1000 » most obvious representation for people » does not allow negative numbers to be directly added » requires separate subtraction hardware 1 111 sign-magnitude arithmetic, left-most bit is sign and remaining bits give magnitude. 11 0000 00 1 10 n In
Computer-Aided Design n CAD tools are essential to the design of complex parts. n Logic design » schematic capture - interactive creation of logic diagrams » hardware description languages - textual representation of circuit function n Design verification » logic simulation to check circuit behavior experimentally » formal verification tools - automated correctness proofs and assertion checking » timing analysis and simulation n Implementation » logic synthesis - convert high level spec. to low level gates » circuit layout - placement of components, routing of wires » details - clock distribution, power, pads, testing 3. 31 - Jon Turner - 1/29/2022
Hardware Description Languages n HDLs allow designers to work at a higher level of abstraction than logic gates. n As with programming languages, HDL descriptions are compiled into a lower level representation. » low level form can be simulated for logical correctness » and, can be converted to a circuit specification using a library of primitive components and timing/area constraints n But don’t confuse hardware design with software. » HDL descriptions must reduce to physical hardware that can be fit in the physical space available and meets timing specs. » hardware designs are inherently parallel with many things going on at once » on the other hand, software can be used to implement much more complex functions than hardware alone. 3. 32 - Jon Turner - 1/29/2022 Read Sections 1, 2 of VHDL Tutorial
VHDL Specification of Half Adder library provides commonly used types and functions Port declaration defines inputs and outputs. STD_LOGIC type used for signals. CAD software simulates circuit operation. May have different implementations for a given module. Signal assignments occur simultaneously. xor, and are builtin operators 3. 33 - Jon Turner - 1/29/2022
VHDL Specification of Full Adder library IEEE; use IEEE. STD_LOGIC_1164. ALL; use IEEE. STD_LOGIC_ARITH. ALL; use IEEE. STD_LOGIC_UNSIGNED. ALL; Compact port entity full. Add is declarations Port ( a, b, Ci : in std_logic; S, Co : out std_logic; ); end full. Add; Complex logic architecture a 1 of full. Add is expressions. begin S <= a xor b xor Ci; Co <= (a and b) or (a and Ci) or (b and Ci); end a 1 3. 34 - Jon Turner - 1/29/2022
What Does VHDL Spec Mean? n VHDL specifies a circuit, not sequential execution. So, architecture arch of fulladd is begin s <= (a xor b) xor Ci; Co <= (a and b) or (a and Ci) or (b and Ci); end arch; means s Co a b Ci n So, what does this mean? architecture foo of bar is begin a <= ‘ 1’; b <= a; a <= ‘ 0’; end bar; 3. 35 - Jon Turner - 1/29/2022
Signal Assignments for Vectors n Example: entity foo is port(a: in std_logic; b: in std_logic_vector(2 downto 0); c: out std_logic_vector(3 downto 0)); end foo; architecture bar of foo is begin c <= a & (b(0) and a) & b(2 downto 1); end bar; defines circuit a b(2) b(1) b(0) c(3) c(2) c(1) c(0) 3. 36 - Jon Turner - 1/29/2022
Conditional Signal Assignment n Example: c <= means "0010" when a /= b else "1101" when a = '1' else "0100"; a b 4 "0010" / 4 "1101" / 4 / c 4 "0100" / n general form x <= v 1 when f 1(a 1, b 1, . . . ) else v 2 when f 2(a 2, b 2, . . . ) else v 3 when f 3(a 3, b 3, . . . ) else. . . else v. N 3. 37 - Jon Turner - 1/29/2022 x <= (f 1(a 1, b 1, . . . ) and v 1) or (not f 1(a 1, b 1, . . . ) and f 2(a 2, b 2, . . . ) and v 2) or (not f 1(a 1, b 1, . . . ) and not f 2(a 2, b 2, . . . ) and f 3(a 3, b 3, . . . ) and v 3) or. . .
Selected Signal Assignment n Example: with x select c <= "0010" when "00" , "1101" when "01" | "10" , “ 1100" when others; means "0010" "1101" "1100" 0 1 2 3 4 / c x n Resulting circuit is more compact and faster than circuit produced by conditional assignment. 3. 38 - Jon Turner - 1/29/2022
Important Characteristics of VHDL n VHDL developed for circuit modelling & simulation. » allows specification of hardware behavior independent of implementation » synthesis tools developed later » not all VHDL specifications can be synthesized n Signals correspond to wires in circuit. » language also supports variables - useful in behavioral models, testbenches » best to avoid variables in synthesizable models – (except loop variables) n Signal assignments define logic circuits. » signals on left side of assignment change as signals on right side change (exceptions to be discussed later) » not like sequential program execution n Strong typing in VHDL. » signal types in expressions must match exactly – no automatic type conversions » bit and integer are only built-in types » extensive support for user-defined types, such as std_logic » std_logic defines 9 values, including 0, 1 and undefined 3. 39 - Jon Turner - 1/29/2022
Processes and if-then-else n Example: process block enables use of entity foo is port( complex statement types a, b: in std_logic; c, d: out std_logic_vector(3 downto 0)); end foo; sensitivity list must architecture foo of bar is begin include all “input” process (a, b) begin signals to process if a /= b then c <= "0010"; d <= "1100"; elsif a = '1' then c <= "1101"; d <= a & b & "01"; else c <= "0100"; d <= "10" & b & a; end if; note that c, d defined under end process; all possible input conditions end foo; REQUIRED 3. 40 - Jon Turner - 1/29/2022
Avoiding Unintended Storage n n If value of a signal is not specified for some condition, it means that signal is unchanged. Example process(a, b) begin if a = '1' then x <= '0'; elsif b = '1' then x <= '1'; end if; -- x retains value when a=b=0 end process; Storage elements are required to implement circuit with the specified behavior. – if one accidentally omits a condition for a signal, unintended storage elements are synthesized. n Easy way to avoid unintended storage is to start process with assignment of default values to all signals assigned a value inside the process. 3. 41 - Jon Turner - 1/29/2022
Default Values n Example: entity foo is port( a, b: in std_logic; c, d: out std_logic_vector(3 downto 0)); end foo; initial assignments architecture foo of bar is begin define “default” values process (a, b) begin for c and d c <= "0100"; d <= "10" & b & a; if a /= b then c <= "0010"; d <= "1100"; elsif a = '1' then c <= "1101"; d <= a & b & "01"; end if; end process; What values are assigned to c, end foo; d if we rearrange so if-then-else comes first? 3. 42 - Jon Turner - 1/29/2022
For-loops entity adder 8 is Port ( Cin : in std_logic; A, B : in std_logic_vector(7 downto 0); S : out std_logic_vector(7 downto 0); Cout : out std_logic); end adder 8; architecture arch 1 of adder 8 is For-loop defines multiple identical (or signal C: std_logic_vector(8 downto 0); similar) sub-circuits. begin Loop does not imply sequential ordering process(A, B, C, Cin) begin of signal assignments. C(0) <= Cin; Cout <= C(8); for i in 0 to 7 loop S(i) <= A(i) xor B(i) xor C(i); C(i+1) <= (A(i) and B(i)) or (A(i) and C(i)) or (B(i) and C(i)); end loop; end process; Note separate carry signal for each stage – end arch 1; cannot re-assign values to one signal as in sequential programs. 3. 43 - Jon Turner - 1/29/2022
Case Statement n Case statement provides convenient way to express alternatives that depend only on value of a single signal architecture a 1 of foo is begin process(c, d, e) begin b <= '1'; -- provide default value for b case e is when "00" => a <= c; b <= d; when "01" => a <= d; b <= c; when "10" => a <= c xor d; when others => a <= '0'; others alternative is required even end case; when all “logical alternatives” are end process; specified end a 1; n Creates more efficient circuits than equivalent if-then-else. 3. 44 - Jon Turner - 1/29/2022
VHDL Spec. for Simple Arithmetic Unit entity alu is Port ( a, b : in std_logic_vector(3 downto 0); c : in std_logic_vector(2 downto 0); x : out std_logic_vector(3 downto 0); v : out std_logic); end alu; architecture a 1 of alu is signal result: std_logic_vector(4 downto 0); signal ax, bx: std_logic_vector(4 downto 0); begin ax <= '0' & a; bx <= '0' & b; result <= ax when c = "000" else bx when c = "001" else (not ax)+1 when c = "010" else (not bx)+1 when c = "011" else ax+bx when c = "100" else ax+bx when c = "101" else ax-bx when c = "110" else bx-ax; x <= result(3 downto 0); v <= '1‘ when (c = "010" and a = "1000") or (c = "011" and b = "1000") or (c = "100" and result(4) = '1') or (c = "101" and a(3) =b(3) and a(3) /= result(3)) or (c = "110" and a(3)/=b(3) and a(3) /= result(3)) or (c = "111" and a(3)/=b(3) and b(3) /= result(3)) else '0'; end a 1; c=0 means x=a, c=1 means x=b, c=2 means x= -a, c=3 means x=-b, c=4 means x=a+b (unsigned), c=5 means x=a+b (signed), c=6 means x=a-b, c=7 means x=b-a 3. 45 - Jon Turner - 1/29/2022 v bit signals arithmetic error
VHDL Spec. for Simple Arithmetic Unit entity alu is Port ( a, b : in std_logic_vector(w. Siz-1 downto 0); c : in std_logic_vector(ctl. Siz-1 downto 0); x : out std_logic_vector(w. Siz-1 downto 0); v : out std_logic); end alu; architecture a 1 of alu is signal result: std_logic_vector(w. Siz downto 0); signal ax, bx: std_logic_vector(w. Siz downto 0); begin ax <= '0' & a; bx <= '0' & b; with c select result <= ax when "000" , bx when "001" , (not ax)+1 when "010" , (not bx)+1 when "011" , ax+bx when "100" , ax+bx when "101" , ax-bx when "110" , bx-ax when others; x <= result(w. Siz-1 downto 0); v <= '1‘ when (c = "010" and a = "1000") or (c = "011" and b = "1000") or (c = "100" and result(w. Siz) = '1') or (c = "101" and a(w. Siz-1) =b(w. Siz-1) and a(w. Siz-1) /= result(w. Siz-1)) or (c = "110" and a(w. Siz-1)/=b(w. Siz-1) and a(w. Siz-1) /= result(w. Siz-1)) or (c = "111" and a(w. Siz-1)/=b(w. Siz-1) and b(w. Siz-1) /= result(w. Siz-1)) else '0'; end a 1; c=0 means x=a, c=1 means x=b, c=2 means x= -a, c=3 means x=-b, c=4 means x=a+b (unsigned), c=5 means x=a+b (signed), c=6 means x=a-b, c=7 means x=b-a v bit signals arithmetic error 3. 46 - Jon Turner - 1/29/2022
Alternate Architecture arithuv_arch of arithuv is signal result: STD_LOGIC_VECTOR(4 downto 0); signal ax, bx: STD_LOGIC_VECTOR(4 downto 0); signal en_a, en_b, neg_a, neg_b: STD_LOGIC; begin process(a, b, c, en_a, en_b, neg_a, neg_b ) begin en_a <= '1'; en_b <= '1'; neg_a <= '0'; neg_b <= '0'; v <= '0'; case c is when "000" => en_b <= '0'; when "001" => en_a <= '0'; when "010" => en_b <= '0'; neg_a <= '1'; if a = "1000" then v <= '1'; end if; when "011" => en_a <= '0'; neg_b <= '1'; if b = "1000" then v <= '1'; end if; when "100" => v <= result(4); - /= a(3) then when "101" => if a(3) = b(3) and result(3) v <= '1'; end if; when "110" => neg_b <= '1'; if a(3) /= b(3) and result(3) /= a(3) then v <= '1'; end if; when "111" => neg_a <= '1'; if a(3) /= b(3) and result(3) /= b(3) then v <= '1'; 3. 47 - Jon Turner - 1/29/2022 end if; case statement specifies alternatives based on signal value. en_a high when a used to generate result. neg_a high to produce a or b-a. others required when not all alternatives listed.
for i in 0 to 3 loop ax(i) <= (a(i) xor neg_a) and en_a; bx(i) <= (b(i) xor neg_b) and en_b; end loop; ax(4) <= en_a and (a(3) xor neg_a); bx(4) <= en_b and (b(3) xor neg_b); result <= ax + bx + (neg_a or neg_b); x <= result(3 downto 0); end process; end arithuv_arch; n n for-loop modifies a, b extend a, b to 5 bits with correct sign Original architecture synthesizes redundant components. Alternative architecture uses single adder and disables or negates inputs to implement different operations. » circuit uses about half as many circuit components as original » synthesis report provides detailed description 3. 48 - Jon Turner - 1/29/2022
Structural Spec. for 4 Bit Adder entity adder 4 is port( Component definitions A, B: in std_logic_vector(3 downto 0); required in every Ci: in std_logic; architecture using a S: out std_logic_vector(3 downto 0); component. Co: out std_logic); end adder 4; architecture a 1 of adder 4 is component statement used to component full. Adder form complex circuits from port(A, B, Ci: in std_logic; S, Co: out std_logic simpler parts. ); end component; signal C: std_logic_vector(4 downto 0); begin C(0) <= Ci; Co <= C(4); b 0: full. Adder port map(A(0), B(0), C(0), S(0), C(1)); b 1: full. Adder port map(A(1), B(1), C(1), S(1), C(2)); b 2: full. Adder port map(A(2), B(2), C(2), S(2), C(3)); b 3: full. Adder port map(A(3), B(3), C(3), S(3), C(4)); end a 1; Positional association of signals. Explicit assignment (A=>A(0)) also allowed. 3. 49 - Jon Turner - 1/29/2022
Defining Constants n To define constants for use by multiple entities, use separate package common. Constants is constant word. Size: integer : = 8; end package common. Constants; library IEEE; use IEEE. . . use work. common. Constants. all; entity adder is port( A, B: in std_logic_vector(word. Size-1 downto 0); Ci: in std_logic; S: out std_logic_vector(word. Size-1 downto 0); Co: out std_logic ); end adder; . . . n Local constants can be declared as part of each architecture. n HDL bencher does not handle constants in packages correctly. » use Options Map Package Constants/Defines 3. 50 - Jon Turner - 1/29/2022
Structural Specs. using for-generate begin C(0) <= Ci; bg: for i in 0 to 3 generate b: fulladder port map(A(i), B(i), C(i), S(i), C(i+1)); end generate; Co <= C(4); for-generate makes it easy to end a 1; generate adder of any size. Note: labels are required. 3. 51 - Jon Turner - 1/29/2022
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