COMBINATIONAL LOGIC Digital Integrated Circuits Combinational Logic Prentice
COMBINATIONAL LOGIC Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Overview Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Combinational vs. Sequential Logic Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Static CMOS Circuit At every point in time (except during the switching transients) each gate output is connected to either VDD or Vss via a low-resistive path. The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Static CMOS Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
NMOS Transistors in Series/Parallel Connection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
PMOS Transistors in Series/Parallel Connection Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Complementary CMOS Logic Style Construction (cont. ) Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Example Gate: NAND Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Example Gate: NOR Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Example Gate: COMPLEX CMOS GATE Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
4 -input NAND Gate Vdd Out GND In 1 In 2 In 3 In 4 Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Standard Cell Layout Methodology Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Two Versions of (a+b). c Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Logic Graph Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Consistent Euler Path Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Example: x = ab+cd Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Properties of Complementary CMOS Gates Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Properties of Complementary CMOS Gates Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Transistor Sizing Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Propagation Delay Analysis - The Switch Model Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
What is the Value of Ron? Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Numerical Examples of Resistances for 1. 2 mm CMOS Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Analysis of Propagation Delay Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Design for Worst Case Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Influence of Fan-In and Fan-Out on Delay Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
tp as a function of Fan-In Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Fast Complex Gate - Design Techniques Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Fast Complex Gate - Design Techniques (2) Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Fast Complex Gate - Design Techniques (3) Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Fast Complex Gate - Design Techniques (4) Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Example: Full Adder Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
A Revised Adder Circuit Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Ratioed Logic Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Ratioed Logic Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Active Loads Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Load Lines of Ratioed Gates Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Pseudo-NMOS Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Pseudo-NMOS NAND Gate VDD GND Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Improved Loads Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Improved Loads (2) Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Example Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Pass-Transistor Logic Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
NMOS-only switch Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Solution 1: Transmission Gate Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Resistance of Transmission Gate Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Pass-Transistor Based Multiplexer S S VDD GND In 1 Digital Integrated Circuits Combinational Logic In 2 © Prentice Hall 1995
Transmission Gate XOR Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Delay in Transmission Gate Networks Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Elmore Delay (Chapter 8) Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Delay Optimization Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Transmission Gate Full Adder Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
(2) NMOS Only Logic: Level Restoring Transistor Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Level Restoring Transistor Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Solution 3: Single Transistor Pass Gate with VT=0 Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Complimentary Pass Transistor Logic Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
4 Input NAND in CPL Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Dynamic Logic Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Example Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Transient Response Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Dynamic 4 Input NAND Gate VDD Out In 1 In 2 In 3 In 4 f Digital Integrated Circuits GND Combinational Logic © Prentice Hall 1995
Reliability Problems — Charge Leakage Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Charge Sharing (redistribution) Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Charge Redistribution - Solutions Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Clock Feedthrough Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Clock Feedthrough and Charge Sharing Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Cascading Dynamic Gates Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Domino Logic Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Domino Logic - Characteristics Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
np-CMOS Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
np CMOS Adder Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
Manchester Carry Chain Adder Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
CMOS Circuit Styles - Summary Digital Integrated Circuits Combinational Logic © Prentice Hall 1995
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