Chapter 8 Main Memory Chapter 8 Memory Management

Chapter 8: Main Memory

Chapter 8: Memory Management n Background n Swapping n Contiguous Memory Allocation n Paging n Structure of the Page Table n Segmentation n Example: The Intel Pentium

Objectives n To provide a detailed description of various ways of organizing memory hardware n To discuss various memory-management techniques, including paging and segmentation n To provide a detailed description of the Intel Pentium, which supports both pure segmentation and segmentation with paging

Background n Program must be brought (from disk) into memory and placed within a process for it to be run n Main memory and registers are only storage CPU can access directly n Register access in one CPU clock (or less) n Main memory can take many cycles n Cache sits between main memory and CPU registers n Protection of memory required to ensure correct operation

Multistep Processing of a User Program

Binding of Instructions and Data to Memory n A program resides on a disk as a binary executable file. n The collection of processes on the disk that is waiting to be brought into memory for execution forms the input queue. n A user program goes through several steps like compile time, load time etc. n Addresses in the source program are generally symbolic( like count). n A compiler will typically bind these symbolic addresses to relocatable addresses (“ 14 bytes from beginning”) n The linkage editor or loader will in turn bind these relocatable addresses to absolute addresses (such as 74014). Each binding is a mapping from one address space to another. n Address binding of instructions and data to memory addresses can happen at three different stages l Compile time: If memory location known a priori, absolute code can be generated; must recompile code if starting location changes l Load time: Must generate relocatable code if memory location is not known at compile time l Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another. Need hardware support for address maps (e. g. , base and limit registers)

Base and Limit Registers n A pair of base and limit registers define the logical address space

Logical vs. Physical Address Space n The concept of a logical address space that is bound to a separate physical address space is central to proper memory management l Logical address – generated by the CPU; also referred to as virtual address l Physical address – address seen by the memory unit n Logical and physical addresses are the same in compile-time and load-time address-binding schemes; logical (virtual) and physical addresses differ in execution-time address-binding scheme

Memory-Management Unit (MMU) n Hardware device that maps virtual to physical address n In MMU scheme, the value in the relocation register is added to every address generated by a user process at the time it is sent to memory n The user program deals with logical addresses; it never sees the real physical addresses

Dynamic relocation using a relocation register

Dynamic Loading n Routine is not loaded until it is called n When a routine needs to call another routine, the calling routine first checks to see whether the other routine has been loaded. If not, the relocatable linking loader is called to load the desired routine into memory and to update the program’s address tables to reflect this change. n Better memory-space utilization; unused routine is never loaded n Useful when large amounts of code are needed to handle infrequently occurring cases. Eg error routines. n No special support from the operating system is required implemented through program design

Dynamic Linking n Linking postponed until execution time n Small piece of code, stub, indicates how to locate the appropriate memory-resident library routine, or how to load the library if the routine is not already present. n Stub replaces itself with the address of the routine, and executes the routine n Operating system needed to check if routine is in processes’ memory address n Dynamic linking is particularly useful for libraries n System also known as shared libraries (the new versions uses the old version libraries if possible)

Overlays n To enable a process to be larger than the amount of memory allocated to it, we can use overlays. n The idea is to keep in memory only the needed programs. n Consider a two pass assembler. Available memory is 150 KB Pass 1 70 KB Pass 2 80 KB Symbol table 20 KB Common routines 30 KB n To load everything we need 200 kb. If only 150 kb is available how to do it? n Thus we can define two overlays : overlay A = pass 1+symbol table+common routines n Overlay b= pass 2 + symbol table + common routines

Symbol table 20 k Pass 1 70 k Common routine 30 k overlay driver 10 k Pass 2 80 k

Swapping n A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution (eg round robin method) n Backing store – fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images Roll out, roll in – swapping variant used for priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executed n Normally a process that is swapped out will be swapped back into the same memory space that it occupied previously. If binding is done at assembly or load time , then the process cannot be moved to different locations. If execution-time binding is being used, then a process can be swapped into a different memory space. n n Major part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swapped Modified versions of swapping are found on many systems (i. e. , UNIX, Linux, and Windows) n System maintains a ready queue of ready-to-run processes which have memory images on disk n Whenever the CPU scheduler decides to execute a process, it calls a dispatcher. n The dispatcher checks to see whether the next process in the queue is in memory. If not, and there is no free memory region, the dispatcher swaps out a process currently in memory and swaps in the desired process. n

Swapping continued n Context-switch is more n Assume a process of size 1 MB and the backing store with a transfer rate of 5 MB per second n Then the context-switch for this will be 1000 KB / 5000 KB per second = 1/5 sec = 200 millisec n Assuming no head seeks and only average latency of 8 millisec the swap time is = 208 millisec When considering swap in and swap out then total swap time= 416 millisec. n For effective CPU utilization, execution time of process should be longer than swap time. n Swap should not take place for a pending I/O process. n Assume that an I/O operation was queued because the device was busy. If process P 1 is swapped out and P 2 is swapped in, the I/O operation might then attempt to use memory that now belongs to process P 2.

Schematic View of Swapping

Contiguous Allocation n Main memory usually divided into two partitions: Resident operating system, usually held in low memory with interrupt vector l User processes then held in high memory l n Relocation registers used to protect user processes from each other, and from changing operating-system code and data l Base register contains value of smallest physical address l Limit register contains range of logical addresses – each logical address must be less than the limit register l MMU maps logical address dynamically l Relocation register scheme provides an effective way to allow the os size to change dynamically. (called transient code) for eg os may be loaded with device driver which may not be used for long time. Such codes can be removed and these spaces can be used by some other process.

HW address protection with base and limit registers

Contiguous Allocation (Cont. ) n The OS keeps a table indicating which parts of memory are available and which are occupied. n Initially all memory is available as one large block (hole) n Multiple-partition allocation Os l Hole – block of available memory; holes of various size are scattered throughout memory l When a process arrives, it is allocated memory from a hole large enough to accommodate it l Operating system keeps a table and maintains information about: a) allocated partitions b) free partitions (hole) OS OS process 5 process 9 process 8 process 2 process 10 process 2

n When a process arrives and needs memory, the system searches this set of holes that is large enough for this process n If the hole is too large; it is split into two and one part is allocated to the process and the other returned to set of holes n When a process terminates, it releases its block of memory which is then placed back in the set of holes n If the new hole is adjacent to other holes, they are merged to form a big hole

Dynamic Storage-Allocation Problem How to satisfy a request of size n from a list of free holes n First-fit: Allocate the first hole that is big enough n Best-fit: Allocate the smallest hole that is big enough; must search entire list, unless ordered by size l Produces the smallest leftover hole n Worst-fit: Allocate the largest hole; must also search entire list l Produces the largest leftover hole First-fit and best-fit better than worst-fit in terms of speed and storage utilization

Fragmentation n External Fragmentation – total memory space exists to satisfy a request, but it is not contiguous n Internal Fragmentation – allocated memory may be slightly larger than requested memory; this size difference is memory internal to a partition, but not being used n Reduce external fragmentation by compaction l Shuffle memory contents to place all free memory together in one large block l Compaction is possible only if relocation is dynamic, and is done at execution time l I/O problem 4 Latch 4 Do job in memory while it is involved in I/O only into OS buffers

Paging n Physical address space of a process can be noncontiguous; process is allocated physical memory whenever the latter is available n Divide physical memory into fixed-sized blocks called frames (size is power of 2, between 512 bytes and 8, 192 bytes) n Divide logical memory into blocks of same size called pages n The backing store is also divided into blocks of same size as frames n Keep track of all free frames n To run a program of size n pages, need to find n free frames and load program n Set up a page table to translate logical to physical addresses n Internal fragmentation

Address Translation Scheme n Address generated by CPU is divided into: l Page number (p) – used as an index into a page table which contains base address of each page in physical memory l Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit page number l page offset p d m-n n For given logical address space 2 m and page size 2 n

Paging Hardware

Paging Model of Logical and Physical Memory

Paging Example Consider an eg Page size=4 bytes and physical memory=32 bytes( 8 pages) Logical address 0 maps to physical address=20(=(5*4)+0) Logical address 3 (page 0 offset 3) maps to 23(=(5*4)+3) Logical address 4 (page 0 offset 0) maps to 24(=(6*4)+0 ) 32 -byte memory and 4 -byte pages

Free Frames Before allocation After allocation The OS maintains a frame table which contains the details like which frame is free or allocated; if allocated to which page of which process etc

§ Implementation of page table Most of the os allocate a page table for each process A pointer to the page table is stored with the other register values in the PCB When the dispatcher removes a process from ready queue , it must reload the user register and define the correct hardware page-table values from the stored user page table. Page table can be implemented with a set of registers. (max of 256 entries)

Implementation of Page Table n n n n n Page table can be kept in registers if the page table entry is small. If the page table entry itself is large then it is kept in main memory Page-table base register (PTBR) points to the page table Page-table length register (PRLR) indicates size of the page table In this scheme every data/instruction access requires two memory accesses. One for the page table and one for the data/instruction. The two memory access problem can be solved by the use of a special fastlookup hardware cache called associative memory or translation lookaside buffers (TLBs) When the entry is found in TLB (hit) the page number and offset and frame number is obtained and only one reference to memory is happened When the entry is not found in TLB (miss) then an access to page table which is stored in memory to get the required frame number and offset so there are two access to memory. This reference may be added to TLB for future reference Some TLBs store address-space identifiers (ASIDs) in each TLB entry – uniquely identifies each process to provide address-space protection for that process

Associative Memory n Associative memory – parallel search Page # Frame # Address translation (p, d) l If p is in associative register, get frame # out l Otherwise get frame # from page table in memory

Paging Hardware With TLB

Effective Access Time n Hit ratio – percentage of times that a page number is found in the associative registers; ratio related to number of associative registers n Example: if 20 nanoseconds needed to search in TLB and 100 nanoseconds to access memory. n Then if the entry is present in TLB it takes =120 nanosec n Else it takes two memory access (one for page table access and get its frame number and again access main memory to search the respective offset=200) = TLB access=20 n Total=200+20=220 nano sec n Effective access time (for a hit)=0. 80*120+0. 20*220= 140 nanosec n For a 98% hit ratio n Effective access time=0. 98*120+0. 02*220=122 nanosec

Memory Protection n Memory protection implemented by associating protection bit with each frame n Valid-invalid bit attached to each entry in the page table: l “valid” indicates that the associated page is in the process’ logical address space, and is thus a legal page l “invalid” indicates that the page is not in the process’ logical address space

Valid (v) or Invalid (i) Bit In A Page Table

Structure of the Page Table n Hierarchical Paging n Hashed Page Tables n Inverted Page Tables

Hierarchical Page Tables n Break up the logical address space into multiple page tables n A simple technique is a two-level page table n Consider a system with a 32 bit logical-address space. n If the page size in such a system is 4 KB (212) then a page table may consist of up to 1 million entries (232/212)=4294967296 / 4096=1048576 (1 MB) n Assuming that each entry consists of 4 bytes (32 bit), each process may need up to 4 MB of physical –address space for the page table alone. n We cannot allocate a single contiguous space for this n So the page table is divided into smaller pieces n Two-level paging is one method where page table itself is paged

Two-Level Paging Example n A logical address (on 32 -bit machine with 1 K page size) is divided into: l a page number consisting of 20 bits a page offset consisting of 12 bits n Since the page table is paged, the page number is further divided into: l a 10 -bit page number l a 12 -bit page offset n Thus, a logical address is as follows: l page number pi 10 page offset p 2 d 10 12 where pi is an index into the outer page table, and p 2 is the displacement within the page of the outer page table

Two-Level Page-Table Scheme

Address-Translation Scheme As address translation works from the outer page table inwards, this scheme is also called as forward-mapped page table

Three-level Paging Scheme

Hashed Page Tables n Common in address spaces > 32 bits n The virtual page number is hashed into a page table. This page table contains a chain of elements hashing to the same location. n Virtual page numbers are compared in this chain searching for a match. If a match is found, the corresponding physical frame is extracted.

Hashed Page Table

Inverted Page Table n General concept of paging l Usually each process has a page table associated with it l The page table has one entry for each page that the process is using n One entry for each real page of memory n Entry consists of the virtual address of the page stored in that real memory location, with information about the process that owns that page n Decreases memory needed to store each page table, but increases time needed to search the table when a page reference occurs n Use hash table to limit the search to one — or at most a few — page -table entries

Inverted Page Table Architecture

Shared Pages n Shared code l One copy of read-only (reentrant) code shared among processes (i. e. , text editors, compilers, window systems). l Shared code must appear in same location in the logical address space of all processes n Private code and data l Each process keeps a separate copy of the code and data l The pages for the private code and data can appear anywhere in the logical address space

Shared Pages Example

Segmentation n Memory-management scheme that supports user view of memory n A program is a collection of segments. A segment is a logical unit such as: main program, procedure, function, method, object, local variables, global variables, common block, stack, symbol table, arrays

User’s View of a Program

Logical View of Segmentation 1 4 1 2 3 4 2 3 user space physical memory space

Segmentation Architecture n Logical address consists of a two tuple: <segment-number, offset>, n Segment table – maps two-dimensional physical addresses; each table entry has: l base – contains the starting physical address where the segments reside in memory l limit – specifies the length of the segment n Segment-table base register (STBR) points to the segment table’s location in memory n Segment-table length register (STLR) indicates number of segments used by a program; segment number s is legal if s < STLR

Segmentation Architecture (Cont. ) n Protection l With each entry in segment table associate: 4 validation bit = 0 illegal segment 4 read/write/execute privileges n Protection bits associated with segments; code sharing occurs at segment level n Since segments vary in length, memory allocation is a dynamic storage-allocation problem n A segmentation example is shown in the following diagram

Segmentation Hardware

Example of Segmentation

Protection and sharing n Instruction part can be defined as non-self-modifying (read-only or read-execute only) n Segments are shared when entries in the segment tables of two different processes point to the same location. Eg sqrt function code can be shared by more than one segments n Sharing segments must have a unique segment number, so that any other segments referring should refer it with this unique number or else problem may arise (if there is any reference to itself is made in the sharing segments)

Sharing of segments

Example: The Intel Pentium n Supports both segmentation and segmentation with paging n CPU generates logical address l Given to segmentation unit 4 Which l produces linear addresses Linear address given to paging unit 4 Which generates physical address in main memory 4 Paging units form equivalent of MMU

Logical to Physical Address Translation in Pentium

Intel Pentium Segmentation

Pentium Paging Architecture

Linear Address in Linux Broken into four parts:

Three-level Paging in Linux

End of Chapter 8