Chapter 8 MemoryManagement Strategies 1 1 3 Logical

Chapter 8 記憶體管理策略 (Memory-Management Strategies) 1

1. 3 邏輯位址空間和實體位址空間 (Logical versus Physical Address Space) n CPU所產生的位址通常稱為邏輯位址(logical address, 也稱為virtual address)， 而記憶體單元所看到的位址(也就是載入到記憶體的記憶體位址暫存器 (memory-address register)之數值)通常叫做實體位址(Physical address)。 Ø Logical and physical addresses are the same in compile-time and load-time address-binding schemes; logical (virtual) and physical addresses differ in executiontime address-binding scheme. 硬體裝置MMU: Memory-Management Unit n The user program deals with logical addresses; it never sees the real physical addresses 6

1. 4 動態載入(Dynamic Loading) q 行程大小受限於實體記憶體大小。要得到較佳之記憶體 空間使用效率，可採行動態載入(dynamic loading)。 q 主程式儲存在主記憶體並執行，當需要呼叫其它程式時， 首先看看此程式是不是已經存在記憶體內，如果不是， 便呼叫重定位 鏈結載入程式(relocatable linking loading)， 將所需要的程式載入主記憶體內，並更新行程位址表的 內容。然後控制就轉移給新的載入程式。 n n Routine is not loaded until it is called Better memory-space utilization; unused routine is never loaded Useful when large amounts of code are needed to handle infrequently occurring cases No special support from the operating system is required implemented through program design 7

1. 5 動態鏈結和共用程式庫(Dynamic Linking and Shared Libraries) q 採用動態鏈結，在程式參用程式庫副程式處做一記號 (stub)，該記號為一小段程式來指示如何去找尋適當的記 憶體常駐程式庫副程式，或是如何載入程式庫副程式(如 果不在記憶體中時)。當執行到記號處時，首先檢查所需 要的副程式是否已經存在記憶體中。如果該副程式不在 記憶體中，程式會將它載入到記憶體中。 n n n Linking postponed until execution time Small piece of code, stub, used to locate the appropriate memoryresident library routine Operating system needed to check if routine is in processes’ memory address Dynamic linking is particularly useful for libraries System also known as shared libraries 8

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3. 連續記憶體配置 (Contiguous Memory 3. 1 記憶體映對和保護(Memory Mapping and Protection) Allocation) n Main memory usually into two partitions: q q n Resident operating system, usually held in low memory with interrupt vector User processes then held in high memory Relocation registers used to protect user processes from each other, and from changing operating-system code and data q q q Base register contains value of smallest physical address Limit register contains range of logical addresses – each logical address must be less than the limit register MMU maps logical address dynamically 11

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n Multiple-partition allocation q q q Hole – block of available memory; holes of various size are scattered throughout memory When a process arrives, it is allocated memory from a hole large enough to accommodate it Operating system maintains information about: a) allocated partitions b) free partitions (hole) OS OS process 5 process 9 process 8 process 2 process 10 process 2 13

n n External Fragmentation – total memory space exists to satisfy a request, but it is not contiguous. Internal Fragmentation – allocated memory may be slightly larger than requested memory; this size difference is memory internal to a partition, but not being used (發生在Paging) Reduce external fragmentation by compaction (聚集) q Shuffle memory contents to place all free memory together in one large block q Compaction is possible only if relocation is dynamic, and is done at execution time 另一解決external fragmentation方法是允許Process的Logical Address Space不連續：分頁(Paging)及分段(Segmentation) 16

4. 分頁(Paging) 4. 1 基本方法(Basic Method) n n n n Logical address space of a process can be noncontiguous. Divide physical memory into fixed-sized blocks called frames (size is power of 2, between 512 and 8, 192 bytes) Divide logical memory into blocks of same size called pages Keep track of all free frames To run a program of size n pages, need to find n free frames and load program Set up a page table to translate logical to physical addresses Internal fragmentation 17

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Address Translation Scheme n Address generated by CPU is divided into: q q Page number (p) – used as an index into a page table which contains base address of each page in physical memory Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit page number q page offset p d m-n n For given logical address space 2 m and page size 2 n 19

0 0 0 1 2 3 p=1 Page: 1 p=2 2 d=3 d=2 3 1 d=2 2 3 4 5 6 m=4 n=2 d=3 7 20

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Free-Frame List New Process 22

4. 2 硬體的支援(Hardware Support) Implementation of Page Table n n n Page table若太大不能放在硬體暫存器，需放在main memory Page-table base register (PTBR分頁表基底暫存器) points to the page table Page-table length register (PTLR分頁表長度暫存器) indicates size of the page table 分頁表儲放在記憶體，其存取資料或指令須要二次記憶體存取。 One for the page table and one for the data/instruction. The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs轉譯旁觀緩 衝器) 23

Associative Memory n Associative memory – parallel search Page # Frame # Address translation (p, d) q q If p is in associative register, get frame # out Otherwise get frame # from page table in memory 24

Paging Hardware With TLB 記憶體 25

有效存取時間(Effective Access Time) n n n Associative Lookup = time unit Assume memory cycle time is 1 microsecond Hit ratio – percentage of times that a page number is found in the associative registers; ratio related to number of associative registers Hit ratio = Effective Access Time (EAT) EAT = (1 + ) + (2 + )(1 – ) =2+ – Ex. Hit Ratio =80%, =20 ns, memory access=100 ns, EAT = (100+20) 0. 8 + (200 + 20) (1 -0. 8) = 140 ns Hit Ratio =98%, =20 ns, memory access=100 ns, EAT = (100+20) 0. 98 + (200 + 20) (1 -0. 98) = 122 ns 26

4. 3 保護(Protection) n Memory protection implemented by associating protection bit with each frame n Valid-invalid bit attached to each entry in the page table: q q “valid” indicates that the associated page is in the process’ logical address space, and is thus a legal page “invalid” indicates that the page is not in the process’ logical address space 27

4. 4 共用分頁(Shared Pages) n Shared code q q n One copy of read-only (reentrant) code shared among processes (i. e. , text editors, compilers, window systems). Shared code must appear in same location in the logical address space of all processes Private code and data q q Each process keeps a separate copy of the code and data The pages for the private code and data can appear anywhere in the logical address space Ex. 有40位同時使用相同編輯軟體(150 K)個人檔案(50 K)，總共需要(150+50)*40=8 M 若將編輯軟體共用，則只需要150+(50*40)=2. 15 M 28

5. 分頁表的結構(Structure of the Page Table) 5. 1 階層式的分頁(Hierarchical Paging) Logical Address為 32 bits，其Page Table需要 220 (假設每一Page為 4 K=212) 若以二層式Paging表示，其Page Table只需要 211 (假設每一Page為 4 K=212) 29

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Logical View of Segmentation 1 4 1 2 3 4 2 3 user space physical memory space 35

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