LABORATOIRE DE BATIMENT MAXWELL B1348 MICROELECTRONIQUE LOUVAINLANEUVE BELGIQUE

LABORATOIRE DE BATIMENT MAXWELL B-1348 MICROELECTRONIQUE LOUVAIN-LA-NEUVE BELGIQUE An Approach to the Design of Analog Fuzzy Logic Controllers in CMOS Technologies: Implementation, Test and Application Carlos Dualibe UCL- June 2001

FUZZY LOGIC: Formalism for codifying Human Reasoning within a Numerical Framework. FUZZY SYSTEM: Model-Free Universal Approximator. Structured Knowledge Base (“if-then” rules) Usefulness: To solve problems that are either difficult to tackle mathematically or where its use provides improved performances and/or simpler implementations. Engineering Applications : (examples) -Process and Environmental Control -Robotics and Automation -Automotive Industrial Applications -Signal and Image Processing -Power Electronics -………… UCL- June 2001 2

Hardware Implementation Choices for Fuzzy Controllers Allocation of the applications in the space [Complexity ; Time Response] Allocation of hardware solutions in the space [Complexity ; Time Response] Intended Target Applications: Signal and Image Processing, Power Electronics UCL- June 2001 3

Why Analog? • Fuzzy Processing is analog in ‘nature’. • Usual applications demand reduced accuracy. • Low Power and/or High Speed • Reduced Complexity: Small area – No need of A/D and D/A to interface Sensors and Actuators • Ideal for Embedded Subsystems. Main Goals of this Work • Comprehensive study of the Analogue Fuzzy Operators • Design and Test of Programmable Architectures for Analogue Fuzzy Controllers Secondary Goal: • To undertake preliminary studies of an embedded Fuzzy Logic application in the field of Signal Processing. UCL- June 2001 4

Fuzzy Controller Architecture and Fuzzy Algorithms R 1: Building Blocks: • Membership Functions • T-Norms ; T-Co. Norms • Consequents R 2: • Defuzzifiers Suits optimal for Hardware Implementation ! Fuzzy Controller UCL- June 2001 5

Membership Functions Circuits: -Trapezoidal Shapes Based on Triode Transconductors TYPE –I: Differential Regulated Cascode Triode Transconductor Circuit : M 1, M 2 Triode Non-Symmetric Diff. Amp. DA 1, DA 2 Transfer Curve: Slope gm Crossover Vk (W/L)Md 1 > (W/L)Md 2 Vds UCL- June 2001 6

Membership Functions Circuits (2): TYPE –II: Single Regulated Cascode Triode Transconductor Transfer Curve: Circuit : M 1 Triode M 2 Saturated Slope gm Knee V 2=Vk + n Vds/2 Vds M 2: Large size transistor aimed for setting a conduction threshold n = Subthreshold slope factor UCL- June 2001 7

Membership Functions (3) : Four Independent Parameters 2 slopes (gm 1, gm 2); 2 Crossover (Vk 1 , Vk 2) Iout 1 Iout 2 gm 1 Vk 1 Io Vin Complementary FMF (CFMF) Vk 2 Io Direct FMF UCL- June 2001

Membership Functions Circuits (4): Comparison against saturated transconductor Analogue Programming: Electrically Tunable Slopes by setting Vds Discrete Programming: large slope range is optimally allowed by a set of (W/L)s: Triode Saturated Small Slopes can be set by using small Vds rather than very long channel Transistors Increased Current Consumption (Differential Amplifiers at the Regulation loop) More sensible to Mismatch (Triode transistors Vds) UCL- June 2001 9

Membership Functions Circuits (6): Full Programmable Compact Fuzzy Partition (Based on [1]) Slopes Vs 1, …Vs 4 - Crossover points Vk 1<Vk 2…<Vk 4 SPICE simulation for a 7 -label Circuit: Io= 10 A, Vdd=5 V Reduced number of transconductors Reduced Current Consumption Cumulative mirroring errors and delay due to cascading [1] Willamosky B. et al, ANNIE’ 96 UCL- June 2001

T-Norm and T-Co. Norm circuits: General Requirements In 1 T-Norm or In. N • Multiple Out T-Co. Norm inputs (N) • O(N) Complexity: Size and consumption proportional to N • Parallel Processing: No cascade tree of binary operators • Inputs Transparency: Same load at each input - Same input/output delay Circuits: - Improved Lazzaro’s WTA-MAXIMUM - Mixed-Mode O(N) MAXIMUM - O(N 2) LTA-MINIMUM - O(N) LTA-MINIMUM UCL- June 2001 11

T-Norm and T-Co. Norm (1): Lazzaro’s WTA-MAXIMUM Improved Version Concept Systematic Errors: ~1. 6% • N current-controlled voltage-sources ( M 1, M 2 ) ‘fighting’ in parallel • Propagation error Early effect in M 2 ( Mo) • Discrimination error: Early effect in M 2 - inversion degree of M 1 • Mismatch error: VT and of M 2, Mo UCL- June 2001

T-Norm and T-Co. Norm (2): Lazzaro’s WTA-MAXIMUM Delay & Undershot Improvement! E I 1=5 A I 2=pulse 3 A to 7 A - 100 ns UCL- June 2001 13

T-Norm and T-Co. Norm (3): Mixed-Mode MAXIMUM Systematic Errors: ~2. 3% • Set of N Source Followers ‘fighting’ in parallel Distribution of Input Signals • Propagation error: Voff = offset of A achievable in voltage-mode !! • Discrimination error: Ao = DC gain of A • Mismatch errors: due to Voff mainly UCL- June 2001

T-Norm and T-Co. Norm (4): New O(N 2) LTA-MINIMUM [2] 2 -Input LTA & MINIMUM 2 -Input MINIMUM Systematic Errors: ~3% • Parallel comparison between input currents -Vdd limits the number of inputs • Propagation error: Due to the Early Effect in transistors Mp • Discrimination error : with the impedance of internal nodes (i. e. : V 2) • Mismatch errors: Associated with mirrors Mn and Mp [2] Dualibe, Jespers, Verleysen, IEEE ISCAS’ 2001 UCL- June 2001

T-Norm and T-Co. Norm (5): New O(N) LTA-MINIMUM [3] Concept Improved Version with current feedback Ii Mirror • N current-controlled voltage sources (Cells-i) ‘fighting’ in parallel • Current feedback improves accuracy of the MINIMUM (~ enhanced Wilson mirror) • Systematic error (~0. 4%) • Mismatch error: due to VT and of M 5, M 6 [3] Donckers, Dualibe, Verleysen, IEEE ISCAS’ 2000 UCL- June 2001

Defuzzifiers : Closed Loop Defuzzifiers Voltage mode • Complexity increases with the number of rules • May need frequency compensation due to feedback: speed Current mode • FMF or T-Norms’ gain must be controlled • May need frequency compensation due to feedback: speed UCL- June 2001

Defuzzifiers(2): Open Loop Defuzzifiers eudo-Normalizer ty may increase with the rules (i. e. : R 1…. Rm) Divider • Only one extra mirror per rule to compute denominator UCL- June 2001

Defuzzifiers(3): Open Loop Defuzzifier with Divider ‘Common Weighting’ strategy for digitally programmable singletons. • ‘n’ mirrors per singleton • Silicon surface and input capacitance of each singleton result much smaller than in the ‘local weighting’ approach (i. e. : (2 n/n) times reduced) • Only one D/A- Can be optimized to get desired accuracy • Simplicity UCL- June 2001

Defuzzifiers(4): Novel Two-Quadrant Analog Divider [4] • M 1= M 2=M 3 triode Input Nodes Nd and Nn become resistive! Thus: Nd Nn Vout-Vbo= (Vb 1 -Vbo) (IN/ k ID) • Current/input voltage/output IDEAL! • Systematic errors: - Mainly due to mobility reduction in triode transistors M 1, M 2, M 3. - Gain error and offset can be neglected if cascoded PMOS mirrors are used (M 7, M 8, M 9). • Mismatch errors: -For small current ID, strongly influence of mismatch of VT between transistors M 4, M 5, M 6. [4] Dualibe, Verleysen, Jespers, IEE Electronics Letters, 1998. UCL- June 2001

Defuzzifiers(5): Two-Quadrant Analog Divider-Measurement (+) Measured (-) Calculated (Vout-Vbo) vs. IN: Relative errors vs. ID: 0< IN <10 A; 10 A< ID <30 A 2 A < IN < 8 A; 10 A< ID <30 A Non-Linearity: UCL- June 2001

Defuzzifiers(6): Comparison Against other Dividers Wiegerink R. , Kluwer A. P. , 1993 • Inputs must be supplied at different nodes at least twice Additional mirroring errors • NL = ~1% Huertas et al, Trans. Fuzzy Systems, 1996 • Need extra I-to-V converter • Differential currents inputs • NL = ~1% (only divider) Current-to-voltage converter Divider UCL- June 2001

Defuzzifiers(7): Electrically Programmable Singletons New Electrically Tunable Linear Current-Mirror Spice Simulation: 1 V<Vb 2<1. 5 V Other Approach: Sasaki et al, 3 th Int. Conf. On Industrial Fuzzy Control and Intelligent Systems 1993 UCL- June 2001

Estimation of the global accuracy of the Controller Only One Fired Rule: 2% < Vout/Vout <3% Unrealistic! Divider Singletons +D/A Mirror Vout UCL- June 2001 % 24

Estimation of the global accuracy of the Controller(2) Two Fired Rules in a complementary way: 2. 5% < Vout/Vout <3. 5% Vout for: 0. 1< 1 < 0. 9 25 2=0. 9 %: (+) Divider UCL- June 2001 25 (o) CFMF+T-Norm+Io

Programmable Fuzzy Architectures: General Guidelines • Standard CMOS Technologies Mixed Signal : Analogue Processing + Digital Programming • Current-Mode vs. Voltage-Mode: Current Mode Voltage Mode Analog Computation: …………. + - Signal Routing……. : …………. . - + Chip external Interface: ………. . - + MIXED MODE • Building Blocks Interface: Avoid the use of extra V-to-I or I-to-V converters Improves Delays and Accuracy. • Modularity: Share operators (i. e: Membership Functions Circuits, Common weighting) • Transistors Sizing: Large size Good Matching Poor Integration Density (dedicated controllers) Small size Poor Matching Good Integration Density (programm. controllers) Programmability can help to relax sizing requirements for a given accuracy! UCL- June 2001

A 9 -Rule 2 -Input 1 -Output Programmable Fuzzy Controller [6] • Zero-Order Controller-Fixed Number of Rules (Grid Partition) • Complementary MF Labels (Type II – Three per input) • T-Norm: Complemented Lazzaro’s MAXIMUM • Defuzzifier: ‘Common weighting’ • Discrete Programming of Antecedents and Consequents • Intended for embedded applications [6] Dualibe, Jespers, Verleysen, IEEE ISCAS’ 2000 UCL- June 2001

9 -Rule Fuzzy Controller (1): Membership Function Programming Linear Resistor • Measured CFMF Type-II: • Io=10 A ; Vdd=5 V Half CFMF Type-II • Input Range: 1. 5 V<Vin<4. 5 V • Local setting of analog parameters • s 0…. . s 3 Slopes (2 x 4 -bit) • p 0…. p 4 Knees (2 x 5 -bit) UCL- June 2001

9 -Rule Fuzzy Controller (2): Test Result TARGET Relative Error Surface MEASURED Relative Error Distribution Settling time (90%): RMSE _max Mean( ) S. Signal: ~190 ns L. Signal: ~450 ns 27 m. V (2. 7%) 62 m. V (6. 2 %) 35 m. V (3. 5%) UCL- June 2001

9 -Rule Fuzzy Controller (3): Comparison [Ke. Sc 93] Complexity [Ma. Fr 96] [Gu. Pe 96] [Ba. Hu 98] [Va. Vi 99] [Du. Ve 00] 9 rules@2 input 13 rules@3 input 9 rules@2 input 16 rules@2 input 9 rules@2 input @1 output @2 output @1 output 3 Bi-CMOS 0. 7 CMOS 2. 4 CMOS 1 CMOS 2. 4 CMOS no data 44 m. W@5 V 550 m. W@10 V 20 m. W@5 V 8. 6 m. W@5 V 13. 4 m. W@5 V no data 550 ns 160 ns 2000 ns 471 ns 450 ns Precision no data RMSE: 3. 33% no data MAX: 4% MAX: 6. 2% Interface currents@ voltages@ voltages@ currents voltages currents voltages 2 2 2 Technology Power Consumption Input to Output Delay (inputs@outputs) 13. 75 mm 1. 9 mm 16. 2 mm 1. 6 mm 4. 5 mm 2 MF Knees: fixed on chip (6 b) off chip on chip (5 b) MF Slopes: fixed on chip (4 b) on chip (2 b) fixed on chip (4 b) Consequents: fixed on chip (6 b) off chip on chip (4 b) on chip (5 b) Area 2 2 Programmability UCL- June 2001

Application Example: Fuzzy Control of a DC/DC “Buck” Converter[9] PWM “duty cycle”: Dp, Di: Highly Nonlinear functions Small Steady-State Error and Fast Settling Time for RL Changes ([9] Franchi E. et al. , IEEE JSSC, June 1998) UCL- June 2001

Application Example(2): Fuzzy Control of a DC/DC “Buck” Converter[10] Optimal Control Surfaces DP: 2 Inputs-1 Output 4 Rules DI: 1 Input-1 Output 4 Rules ([10] Rashid M. , Power Electronics-Circuits, Devices and Applications, Prentice Hall, 1993) UCL- June 2001

A General-Purpose Programmable and Reconfigurable Fuzzy Controller N 5; Q 3; M 27; F 16 • CFMF type-II • Programmable MAXIMUM mixed mode O(N) UCL- June 2001 • SWITCH MATRIX: ‘smartly’ wired

General-Purpose Controller (2): First-Order Output Configuration Divider Consequent Rule-i Novel High-Input Impedance Voltage Mode Adder: Defuzzified V alue UCL- June 2001

General-Purpose Controller (3): Zero-Order Test Result Rules Map Measured Surface Relative Errors a) b) Surface RMSE _max Mean( ) Settling time (90%): S. Signal: 570 ns a) 80 m. V (4%) 180 m. V (9 %) 64 m. V (3. 2%) b) 94 m. V (4. 7%) 240 m. V (12 %) 75 m. V (3. 75%) UCL- June 2001 L. Signal: 1100 ns

General-Purpose Controller (4): 4 -rules First-Order Controller Test Result Measured CFMF Measured Surface ANFIS Fitting: A comparison • 1 st-Order; 4 -rules • Zero-Order; 9 -rules • 28 parameters • 20 parameters • 33 parameters • RMSE: 0. 8% • RMSE: 2% • RMSE: 1. 4% UCL- June 2001

COMPARISON UCL- June 2001

General Purpose Controller (6): Further Improvements • Scaling to Modern Technologies: A) Analog Circuits: Cox Early AVTo CMOS 2. 4 50 A/V 10 V/ 24 m. V CMOS 0. 8 100 A/V 10 V/ 12 m. V Silicon Area Same Current Same Vdd, VTo 2 2 -Same L (keep same Early) -W W/2 ===>50% Area Reduction Mismatch B) Digital Circuits: theoretical scaling factor: (1/9). Let us assume (1/4. 5). Total Area Reduction: 39. 5 mm 2 == 13. 6 mm 2 UCL- June 2001

Time-Domain Signal Analysis Using Fuzzy Logic and its Application to Self-Adaptive Channel Equalization General Setup Built-in ‘Oscilloscope’: inferred Assertions could be used for adaptation, detection, testing, etc. UCL- June 2001 39

Continuous-Time Self-Adaptive Equalization based on the Eye-Pattern [8]: System Architecture A) E(s) = (s-z) (s+z) Adaptive Equalizing System • On-Chip Real-Time Scope: B) Control Surface related to the Eye Pattern SIGNAL 2 D-FIGURE (EYE PATTERN) • Controller’s Decision Making : “Keep ACTUAL EYE within AREA TOLERANCE” • Controller’s Output: [8] Dualibe, Jespers, Verleysen, IEEE ISCAS’ 2001 EQUALIZER’S ZEROS PLACEMENT UCL- June 2001 40

Fuzzy Logic Controller : Rule Base and Input Partition Boosting must Increase Area Tolerance Boosting must Decrease • RULE BASE: 25 -Rules controlling Equalizer Amplitude Boosting (5 -labels per input) • Area Tolerance: immunity to NOISE, RINGING, PULSE SHAPE, ETC UCL- June 2001 41

Architecture of the Fuzzy Controller • Zero-Order Sugeno : 25 rules • Fuzzifiers: 5 -Labels per input. • T-Norms: 2 -input MINIMUM (O(N 2) ) • Defuzzifier: Averaged Weighted Sum • Discrete Programming of singletons (5 -bits) UCL- June 2001 42

5 -Labels Fuzzy Partition Circuit Vin SPICE simulation for Io=10 A • Chained differential pairs: low consuming, small area and compactness • Vk 1<Vk 2<…. . <Vk 4 fix the crossover points • Fixed slopes at mask level by transistors Ma size UCL- June 2001 43

Fuzzy Controller Test Results Fuzzy Logic Controller Measured Technology: CMOS-2. 4 Complexity: 25 -Rules; 2 -inputs; 1 -output Power Supply: 5 V Power Consumption: 4. 4 m. W Area: RMSE: Analog: 2. 9 mm 2 Digital: 1. 1 mm 2 4. 5% Input/Output Delay S. Signal: 380 ns (90% Steady State): L. Signal: 900 ns Target UCL- June 2001 44

Fuzzy Controller: Improvement Vs R 1 R 3 R 2 R 4 R 5 R 6 R 7 R 8 R 9 R 10 R 11 Vt • Use Tree Partition for the input space to minimize rules set ONLY 11 Rules • Input Vs Compact 5 -Label Fuzzy partition circuit • Input Vt Six individual Membership Functions UCL- June 2001

Amplitude-Boosting Gm-C Filter Bi-Quad Filter: A) Amplitude Phase • gm 1=gm 3=gm 5=gmmax fix • gm 2=gm 4 tunable up to gmmax Symmetric Zeros at: Theoretical Frequency Response UCL- June 2001 46

New Full Electrically Tunable Triode Transconductor [9] Transconductance: • Linear tuning Iz • Phase error < 2° Transconductor: Divider: CMFB with adaptive Bias Io [10] Improved common-mode voltage stability upon tuning. CMFB [9] Dualibe, Jespers Verleysen IEEE ISCAS’ 2001 UCL- June 2001 47 [10] De. Lima, Dualibe, IEEE ISCAS’ 2000

Equalizing Filter Test Results Bi. Quad Gm-C filter Technology: CMOS-2. 4 Power Supply: 5. 5 V Power Consumption: 22. 6 m. W (nominal) (Iz=25 A ) Area: 5. 3 mm 2 Max. Boost : 30 d. B (@7 Mhz. ) Tuning range: 15 A< Iz < 35 A Measured AC Response UCL- June 2001 48

Cable Equalization (simulations) A 1) Signals for L=360 m Fs = 5 Mb/s A 2) B 1) Kz evolution for L=120, 240, 360 m B 2) Eye Pattern: before and after the equalizer Cable: CAT 5 UTP UCL- June 2001 49

Adaptation Performance for Noisy Channels Kz Evolution during adaptation Our Approach Widrow [85] Noise: Mean=0 -Variance=0. 03 UCL- June 2001 50

Self-Adaptive Equalization: Conclusions • Robust Adaptive Equalization: Area Tolerance filters out noise, ringing, etc. • Fuzzy Logic Allows easily the Analog Implementation of highly non-linear control functions. • Time-Domain Signal Analysis using Fuzzy Reasoning = On-Chip ‘Oscilloscope’ Applications beyond Channel Equalization topic: ………detection, on-chip analog testing, etc UCL- June 2001 51

CONCLUSIONS: Fuzzy Logic & Non-Linear Analogue Design • Systematic Approach for Analogue Non-Linear Synthesis. • Very Easy to Understand! • Available Optimization and Design Tools (i. e. : ANFIS). • Invariant Network Structure independent on the function to synthesize (i. e: “if-then rules”). • Possibility of programmable devices built by standard blocks (Fuzzifiers, Inference Operators and Defuzzifiers). Fuzzy Logic must take a place in the Toolbox of Analogue Designers for the synthesis of non-linear circuits!! UCL- June 2001