Intro to Microarchitecture SingleCycle CS 3330 Samira Khan

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Intro to Microarchitecture: Single-Cycle CS 3330 Samira Khan University of Virginia Feb 14, 2017

Intro to Microarchitecture: Single-Cycle CS 3330 Samira Khan University of Virginia Feb 14, 2017

AGENDA • Review from last lecture • Single-cycle microarchitecture • Evaluation of single-cycle microarchitecture

AGENDA • Review from last lecture • Single-cycle microarchitecture • Evaluation of single-cycle microarchitecture 2

Recap of Last Week • ISA basics and tradeoffs • • • Instruction length

Recap of Last Week • ISA basics and tradeoffs • • • Instruction length Uniform vs. non-uniform decode Number of registers Addressing modes RISC vs. CISC properties 3

A Note on RISC vs. CISC • Usually, … • RISC • • Simple

A Note on RISC vs. CISC • Usually, … • RISC • • Simple instructions Fixed length Uniform decode Few addressing modes • CISC • • Complex instructions Variable length Non-uniform decode Many addressing modes 4

Y 86 -64 Instruction Set #1 Byte 0 halt 0 0 nop 1 0

Y 86 -64 Instruction Set #1 Byte 0 halt 0 0 nop 1 0 cmov. XX r. A, r. B 2 fn r. A r. B irmovq V, r. B 3 0 F rmmovq r. A, D(r. B) 4 0 r. A r. B D mrmovq D(r. B), r. A 5 0 r. A r. B D OPq r. A, r. B 6 fn r. A r. B j. XX Dest 7 fn Dest call Dest 8 0 ret 9 0 pushq r. A A 0 r. A F popq r. A B 0 r. A F 1 2 3 4 5 6 7 8 9 r. B V Dest 5

A Very Basic Instruction Processing Engine • Single-cycle machine Combinational Logic AS’ (State) AS

A Very Basic Instruction Processing Engine • Single-cycle machine Combinational Logic AS’ (State) AS • What is the clock cycle time determined by? • What is the critical path of the combinational logic determined by? 6

Instruction Processing “Stage” • Instructions are processed under the direction of a “control unit”

Instruction Processing “Stage” • Instructions are processed under the direction of a “control unit” step by step. • Instruction stage: Sequence of steps to process an instruction • Fundamentally, there are five phases: • • • Fetch Decode Execute Memory Store Result • Not all instructions require all stages 7

Single-cycle vs. Multi-cycle: Control & Data • Single-cycle machine: • Control signals are generated

Single-cycle vs. Multi-cycle: Control & Data • Single-cycle machine: • Control signals are generated in the same clock cycle as the one during which data signals are operated on • Everything related to an instruction happens in one clock cycle (serialized processing) • Multi-cycle machine: • Control signals needed in the next cycle can be generated in the current cycle • Latency of control processing can be overlapped with latency of datapath operation (more parallelism) 8

A Single-Cycle Microarchitecture A Closer Look

A Single-Cycle Microarchitecture A Closer Look

Let’s Start with the State Elements Reg Write • Data and control inputs val.

Let’s Start with the State Elements Reg Write • Data and control inputs val. A src. A PC A Register file val. B src. B 0 val. W MUX W dst. W 1 B MUX Select Mem Write Instr Address Instruction Mem Write Data Mem Operation Read Data A B A L U 10

Instruction Processing • 6 (5) generic steps • • • Instruction fetch (IF) Instruction

Instruction Processing • 6 (5) generic steps • • • Instruction fetch (IF) Instruction decode and register operand fetch (ID/RF) Execute/Evaluate memory address (EX/AG) Memory operand fetch (MEM) Store/writeback result (WB) PC Update IF EX/AG ID/RF r. B new PC P C Instr Addr Instruction Mem r. A Dest. E Val. E val. B Val. A Register file A L U MEM Read Data Address Write Data WB Data Mem 11

Instruction Processing • 6 (5) generic steps • • • Instruction fetch (IF) Instruction

Instruction Processing • 6 (5) generic steps • • • Instruction fetch (IF) Instruction decode and register operand fetch (ID/RF) Execute/Evaluate memory address (EX/AG) Memory operand fetch (MEM) Store/writeback result (WB) PC Update IF r. B new PC P C EX/AG ID/RF Instr Addr Instruction Mem r. A Dest. E Val. E val. B Val. A Register file A L U MEM Read Data Address Write Data WB Data Mem 12

Instruction Processing • 6 (5) generic steps • • • Instruction fetch (IF) Instruction

Instruction Processing • 6 (5) generic steps • • • Instruction fetch (IF) Instruction decode and register operand fetch (ID/RF) Execute/Evaluate memory address (EX/AG) Memory operand fetch (MEM) Store/writeback result (WB) PC Update IF r. B new PC P C EX/AG ID/RF Instr Addr Instruction Mem r. A Dest. E Val. E val. B Val. A Register file A L U MEM Read Data Address Write Data WB Data Mem 13

Instruction Processing • 6 (5) generic steps • • • Instruction fetch (IF) Instruction

Instruction Processing • 6 (5) generic steps • • • Instruction fetch (IF) Instruction decode and register operand fetch (ID/RF) Execute/Evaluate memory address (EX/AG) Memory operand fetch (MEM) Store/writeback result (WB) PC Update IF r. B new PC P C EX/AG ID/RF Instr Addr Instruction Mem r. A Dest. E Val. E val. B Val. A Register file A L U MEM Read Data Address Write Data WB Data Mem 14

Single-Cycle Datapath for Arithmetic and Logical Instructions

Single-Cycle Datapath for Arithmetic and Logical Instructions

Executing Arith. /Logical Operation OPq r. A, r. B • Fetch 6 fn r.

Executing Arith. /Logical Operation OPq r. A, r. B • Fetch 6 fn r. A r. B • Memory • Read 2 bytes • Decode • Do nothing • Write back • Read operand registers • Execute • Update register • PC Update • Perform operation • Set condition codes • Increment PC by 2 if MEM[PC] == OPq r. A, r. B R[r. B] op R[r. A] PC + 2 16

Stage Computation: Arith/Log. Ops Fetch Decode Execute Memory Write OPq r. A, r. B

Stage Computation: Arith/Log. Ops Fetch Decode Execute Memory Write OPq r. A, r. B icode: ifun M 1[PC] r. A: r. B M 1[PC+1] val. P PC+2 val. A R[r. A] val. B R[r. B] val. E val. B OP val. A Set CC R[r. B] val. E back PC update PC val. P Read instruction byte Read register byte Compute next PC Read operand A Read operand B Perform ALU operation Set condition code register Write back result Update PC • Formulate instruction execution as sequence of simple steps • Use same general form for all instructions 17

ALU Datapath Reg Write r. A P C Instr Addr Instruction Mem 2 r.

ALU Datapath Reg Write r. A P C Instr Addr Instruction Mem 2 r. B Dest. E Val. E val. A Val. B ALU OP A L U Read Data Address Register file Write Data Mem EX MEM WB A DD if MEM[PC] == OPq r. A, r. B R[r. B] op R[r. A] PC + 2 **Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED. ] IF ID PC Combinational state update logic 18

ALU Datapath Reg Write r. A P C Instr Addr Instruction Mem 2 r.

ALU Datapath Reg Write r. A P C Instr Addr Instruction Mem 2 r. B Dest. E Val. E val. A Val. B ALU OP A L U Read Data Address Register file Write Data Mem EX MEM WB A DD if MEM[PC] == OPq r. A, r. B R[r. B] op R[r. A] PC + 2 **Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED. ] IF ID PC Combinational state update logic 19

Single-Cycle Datapath for Data Movement Instructions

Single-Cycle Datapath for Data Movement Instructions

Executing mrmovq (Load from Mem to Reg) mrmovq D(r. B) , r. A 6

Executing mrmovq (Load from Mem to Reg) mrmovq D(r. B) , r. A 6 fn r. A r. B D • Fetch • Read 10 bytes • Decode • Read operand registers • Execute • Compute effective address • Memory • Read from memory • Write back • Write to Register • PC Update • Increment PC by 10 if MEM[PC]== mrmovq Disp (r. B), r. A EA = Disp + R[r. B] R[r. A] MEM[EA] PC + 10 21

Stage Computation: mrmovq D(r. B), r. A icode: ifun M 1[PC] r. A: r.

Stage Computation: mrmovq D(r. B), r. A icode: ifun M 1[PC] r. A: r. B M 1[PC+1] val. C M 8[PC+2] val. P PC+10 Read instruction byte Read register byte Read displacement D Compute next PC val. B R[r. B] val. E val. B + val. C Read operand B Compute effective address Memory Write val. M M 8[val. E] R[r. A] val. M Write value to memory back PC update PC val. P Update PC Fetch Decode Execute • Use ALU for address computation if MEM[PC]== mrmovq Disp (r. B), r. A EA = Disp + R[r. B] R[r. A] MEM[EA] PC + 10 22

Ld Datapath Reg Write val. B r. B P C Instr Addr Instruction Mem

Ld Datapath Reg Write val. B r. B P C Instr Addr Instruction Mem r. B M U r. A X r. A Dest. E Val. E ALU OP A L U M U X Val. A Register file Read Data Address Write Data Mem MEM WB PC D 10 A DD if MEM[PC]== mrmovq Disp (r. B), r. A EA = Disp + R[r. B] R[r. A] MEM[EA] PC + 10 M U X From ALU From Mem MUX Select IF ID EX Combinational state update logic 23

Ld Datapath: Calculate the Effective Address Reg Write val. B r. B P C

Ld Datapath: Calculate the Effective Address Reg Write val. B r. B P C Instr Addr Instruction Mem r. B M U r. A X r. A Dest. E Val. E ALU OP A L U M U X Val. A Register file Read Data Address Write Data Mem MEM WB PC D 10 A DD if MEM[PC]== mrmovq Disp (r. B), r. A EA = Disp + R[r. B] R[r. A] MEM[EA] PC + 10 M U X From ALU From Mem MUX Select IF ID EX Combinational state update logic 24

Ld Datapath: Loaded memory needs to be written to the Register File. Reg Write

Ld Datapath: Loaded memory needs to be written to the Register File. Reg Write val. B r. B P C Instr Addr Instruction Mem r. B M U r. A X r. A Dest. E Val. E ALU OP A L U M U X Val. A Register file Read Data Address Write Data Mem MEM WB PC D 10 A DD if MEM[PC]== mrmovq Disp (r. B), r. A EA = Disp + R[r. B] R[r. A] MEM[EA] PC + 10 M U X From ALU From Mem MUX Select IF ID EX Combinational state update logic 25

Ld Datapath: Need the Destination Register Reg Write val. B r. B P C

Ld Datapath: Need the Destination Register Reg Write val. B r. B P C Instr Addr Instruction Mem r. B M U r. A X r. A Dest. E Val. E ALU OP A L U M U X Val. A Register file Read Data Address Write Data Mem MEM WB PC D 10 A DD if MEM[PC]== mrmovq Disp (r. B), r. A EA = Disp + R[r. B] R[r. A] MEM[EA] PC + 10 M U X From ALU From Mem MUX Select IF ID EX Combinational state update logic 26

Ld Datapath: Update PC Reg Write val. B r. B P C Instr Addr

Ld Datapath: Update PC Reg Write val. B r. B P C Instr Addr Instruction Mem r. B M U r. A X r. A Dest. E Val. E ALU OP A L U M U X Val. A Register file Read Data Address Write Data Mem MEM WB PC D 10 A DD if MEM[PC]== mrmovq Disp (r. B), r. A EA = Disp + R[r. B] R[r. A] MEM[EA] PC + 10 M U X From ALU From Mem MUX Select IF ID EX Combinational state update logic 27

Executing rmmovq (St from reg to Memory) rmmovq r. A, D(r. B) 4 0

Executing rmmovq (St from reg to Memory) rmmovq r. A, D(r. B) 4 0 r. A r. B D • Fetch • Read 10 bytes • Decode • Read operand registers • Execute • Compute effective address • Memory • Write to memory • Write back • Do nothing • PC Update • Increment PC by 10 if MEM[PC]== rmmovq r. A, Disp (r. B) EA = Disp + R[r. B] MEM[EA] R[r. A] PC + 10 28

Stage Computation: rmmovq r. A, D(r. B) Fetch Decode Execute Memory Write back PC

Stage Computation: rmmovq r. A, D(r. B) Fetch Decode Execute Memory Write back PC update icode: ifun M 1[PC] r. A: r. B M 1[PC+1] val. C M 8[PC+2] val. P PC+10 val. A R[r. A] val. B R[r. B] val. E val. B + val. C Read instruction byte Read register byte Read displacement D Compute next PC Read operand A Read operand B Compute effective address M 8[val. E] val. A Write value to memory PC val. P Update PC • Use ALU for address computation if MEM[PC]== rmmovq r. A, Disp (r. B) EA = Disp + R[r. B] MEM[EA] R[r. A] PC + 10 29

St Datapath Reg Write P C Instr Addr Instruction Mem r. B M U

St Datapath Reg Write P C Instr Addr Instruction Mem r. B M U r. A X r. A Dest. E Val. E ALU OP val. B r. B Mem Write A L U M U X Val. A Register file Read Data Address Write Data Mem MEM WB PC D 10 A DD if MEM[PC]== rmmovq r. A, Disp (r. B) EA = Disp + R[r. B] MEM[EA] R[r. A] PC + 10 M U X From ALU From Mem MUX Select IF ID EX Combinational state update logic 30

St Datapath: Calculate the effective address Reg Write P C Instr Addr Instruction Mem

St Datapath: Calculate the effective address Reg Write P C Instr Addr Instruction Mem r. B M U r. A X r. A Dest. E Val. E ALU OP val. B r. B Mem Write A L U M U X Val. A Register file Read Data Address Write Data Mem MEM WB PC D 10 A DD if MEM[PC]== rnmovq r. A, Disp (r. B) EA = Disp + R[r. B] MEM[EA] R[r. A] PC + 10 M U X From ALU From Mem MUX Select IF ID EX Combinational state update logic 31

St Datapath: Store data needs to reach memory Reg Write P C Instr Addr

St Datapath: Store data needs to reach memory Reg Write P C Instr Addr Instruction Mem r. B M U r. A X r. A Dest. E Val. E ALU OP val. B r. B Mem Write A L U M U X Val. A Register file Read Data Address Write Data Mem MEM WB PC D 10 A DD if MEM[PC]== rnmovq r. A, Disp (r. B) EA = Disp + R[r. B] MEM[EA] R[r. A] PC + 10 M U X From ALU From Mem MUX Select IF ID EX Combinational state update logic 32

St Datapath: Update PC Reg Write P C Instr Addr Instruction Mem r. B

St Datapath: Update PC Reg Write P C Instr Addr Instruction Mem r. B M U r. A X r. A Dest. E Val. E ALU OP val. B r. B Mem Write A L U M U X Val. A Register file Read Data Address Write Data Mem MEM WB PC D 10 A DD if MEM[PC]== rnmovq r. A, Disp (r. B) EA = Disp + R[r. B] MEM[EA] R[r. A] PC + 10 M U X From ALU From Mem MUX Select IF ID EX Combinational state update logic 33

Executing irmovq (Move imm to Reg) irmovq V, r. B 3 0 F r.

Executing irmovq (Move imm to Reg) irmovq V, r. B 3 0 F r. B V • Fetch • Read 10 bytes • Decode • Read operand registers • Execute • Add 0 to V • Memory • Do nothing • Write back • Write V to r. B • PC Update • Increment PC by 10 if MEM[PC]== irmovq V, r. B R[r. B] V + 0 PC + 10 34

Stage Computation: irmovq V, r. B Fetch icode: ifun M 1[PC] r. A: r.

Stage Computation: irmovq V, r. B Fetch icode: ifun M 1[PC] r. A: r. B M 1[PC+1] val. C M 8[PC+2] val. P PC+10 Read instruction byte Read register byte Read displacement D Compute next PC val. E 0 + val. C Compute effective address R[r. B] val. A Write value to memory PC val. P Update PC Decode Execute Memory Write back PC update • Use ALU for address computation if MEM[PC]== irmovq V, r. B R[r. B] V + 0 PC + 10 35

irmov Datapath: Option 1 Reg Write val. B r. B P C Instr Addr

irmov Datapath: Option 1 Reg Write val. B r. B P C Instr Addr Instruction Mem r. B M U r. A X r. A Dest. E Val. E M ALU U OP X 0 M U X Val. A Register file Mem Write A L U Read Data Address Write Data Mem MEM WB PC D 10 A DD if MEM[PC]== irmovq V, r. B R[r. B] V + 0 PC + 10 M U X MUX Select From ALU From Mem IF ID EX Combinational state update logic 36

irmov Datapath Option 1: read register and add zero Reg Write val. B r.

irmov Datapath Option 1: read register and add zero Reg Write val. B r. B P C Instr Addr Instruction Mem r. B M U r. A X r. A Dest. E Val. E M ALU U OP X 0 M U X Val. A Register file Mem Write A L U Read Data Address Write Data Mem MEM WB PC D 10 A DD if MEM[PC]== irmovq V, r. B R[r. B] V + 0 PC + 10 M U X MUX Select From ALU From Mem IF ID EX Combinational state update logic 37

irmov Datapath Option 1: Writeback value Reg Write val. B r. B P C

irmov Datapath Option 1: Writeback value Reg Write val. B r. B P C Instr Addr Instruction Mem r. B M U r. A X r. A Dest. E Val. E M ALU U OP X 0 M U X Val. A Register file Mem Write A L U Read Data Address Write Data Mem MEM WB PC D 10 A DD if MEM[PC]== irmovq V, r. B R[r. B] V + 0 PC + 10 M U X MUX Select From ALU From Mem IF ID EX Combinational state update logic 38

irmov Datapath Option 1: Writeback value Reg Write val. B r. B P C

irmov Datapath Option 1: Writeback value Reg Write val. B r. B P C Instr Addr Instruction Mem r. B M U r. A X r. A Dest. E Val. E M ALU U OP X 0 M U X Val. A Register file Mem Write A L U Read Data Address Write Data Mem MEM WB PC D 10 A DD if MEM[PC]== irmovq V, r. B R[r. B] V + 0 PC + 10 M U X MUX Select From ALU From Mem IF ID EX Combinational state update logic 39

irmov Datapath Option 1: Update PC Reg Write val. B r. B P C

irmov Datapath Option 1: Update PC Reg Write val. B r. B P C Instr Addr Instruction Mem r. B M U r. A X r. A Dest. E Val. E M ALU U OP X 0 M U X Val. A Register file Mem Write A L U Read Data Address Write Data Mem MEM WB PC D 10 A DD if MEM[PC]== irmovq V, r. B R[r. B] V + 0 PC + 10 M U X MUX Select From ALU From Mem IF ID EX Combinational state update logic 40

irmov Datapath Option 2 Reg Write P C Instr Addr Instruction Mem r. B

irmov Datapath Option 2 Reg Write P C Instr Addr Instruction Mem r. B M U r. A X r. A Dest. E Val. E ALU OP val. B r. B Mem Write A L U M U X Val. A Register file Read Data Address Write Data Mem MEM WB PC D 10 A DD if MEM[PC]== irmovq V, r. B R[r. B] V PC + 10 M U X MUX Select From ALU From Mem IF ID EX Combinational state update logic 41

irmov Datapath: Option 2 Reg Write P C Instr Addr Instruction Mem r. B

irmov Datapath: Option 2 Reg Write P C Instr Addr Instruction Mem r. B M U r. A X r. A Dest. E Val. E ALU OP val. B r. B Mem Write A L U M U X Val. A Register file Read Data Address Write Data Mem MEM WB PC D 10 A DD if MEM[PC]== irmovq V, r. B R[r. B] V PC + 10 M U X MUX Select From ALU From Mem IF ID EX Combinational state update logic 42

 • Tradeoffs between option 1 and option 2? • • Extra 2 -to-1

• Tradeoffs between option 1 and option 2? • • Extra 2 -to-1 MUX? 3 -to-1 MUX? What is the cost for n-to-1 MUX? Wire length? Generality? 43

Executing rrmovq (Move from Reg to Reg) rrmovq r. A, r. B 2 0

Executing rrmovq (Move from Reg to Reg) rrmovq r. A, r. B 2 0 r. A r. B • Fetch • Read 2 bytes • Decode • Read operand register r. A • Execute • Add 0 to val r. A • Memory • Do nothing • Write back • Write val r. A to r. B • PC Update • Increment PC by 2 if MEM[PC]== rrmovq r. A, r. B R[r. B] R[r. A] + 0 PC + 2 44

Stage Computation: rrmovq r. A, r. B Fetch Decode Execute icode: ifun M 1[PC]

Stage Computation: rrmovq r. A, r. B Fetch Decode Execute icode: ifun M 1[PC] r. A: r. B M 1[PC+1] val. P PC+2 Read instruction byte Read register byte Read displacement D Compute next PC Val. A R[r. A] val. E 0 + val. A Compute effective address Memory Write R[r. B] val. E back PC update PC val. P Write value to memory Update PC if MEM[PC]== rrmovq r. A, r. B R[r. B] R[r. A] + 0 PC + 2 45

rrmov Datapath: Option 1 Reg Write val. B r. B P C Instr Addr

rrmov Datapath: Option 1 Reg Write val. B r. B P C Instr Addr Instruction Mem r. B M U r. A X r. A Dest. E Val. E M ALU U OP X 0 M U X Val. A Register file Mem Write A L U Read Data Address Write Data Mem MEM WB PC D 2 A DD if MEM[PC]== rrmovq r. A, r. B R[r. B] R[r. A] + 0 PC + 2 M U X From ALU From Mem MUX Select IF ID EX Combinational state update logic 46

rrmov Datapath: Option 1 Reg Write val. B r. B P C Instr Addr

rrmov Datapath: Option 1 Reg Write val. B r. B P C Instr Addr Instruction Mem r. B M U r. A X r. A Dest. E Val. E M ALU U OP X 0 M U X Val. A Register file Mem Write A L U Read Data Address Write Data Mem MEM WB PC D 2 A DD if MEM[PC]== rrmovq r. A, r. B R[r. B] R[r. A] + 0 PC + 2 M U X From ALU From Mem MUX Select IF ID EX Combinational state update logic 47

rrmov Datapath: Option 1 Reg Write val. B r. B P C Instr Addr

rrmov Datapath: Option 1 Reg Write val. B r. B P C Instr Addr Instruction Mem r. B M U r. A X r. A Dest. E Val. E M ALU U OP X 0 M U X Val. A Register file Mem Write A L U Read Data Address Write Data Mem MEM WB PC D 2 A DD if MEM[PC]== rrmovq r. A, r. B R[r. B] R[r. A] + 0 PC + 2 M U X From ALU From Mem MUX Select IF ID EX Combinational state update logic 48

rrmov Datapath: Option 1 Reg Write val. B r. B P C Instr Addr

rrmov Datapath: Option 1 Reg Write val. B r. B P C Instr Addr Instruction Mem r. B M U r. A X r. A Dest. E Val. E M ALU U OP X 0 M U X Val. A Register file Mem Write A L U Read Data Address Write Data Mem MEM WB PC D 2 A DD if MEM[PC]== rrmovq r. A, r. B R[r. B] R[r. A] + 0 PC + 2 M U X From ALU From Mem MUX Select IF ID EX Combinational state update logic 49

rrmov Datapath: Option 2 Reg Write P C Instr Addr Instruction Mem r. B

rrmov Datapath: Option 2 Reg Write P C Instr Addr Instruction Mem r. B M U r. A X D 10 A DD if MEM[PC]== rrmovq r. A, r. B R[r. B] R[r. A] PC + 2 r. A Dest. E Val. E ALU OP val. B r. B Register file ? MUX Select A L U M U X Val. A M U X Mem Write Read Data Address Write Data Mem MEM WB PC From ALU From Mem IF ID EX Combinational state update logic 50

Single-Cycle Datapath for Control Flow Instructions

Single-Cycle Datapath for Control Flow Instructions

Executing Jumps j. XX Dest 7 fn Dest fall thru: XX XX target: Not

Executing Jumps j. XX Dest 7 fn Dest fall thru: XX XX target: Not taken XX XX • Fetch • Read 9 bytes • Increment PC by 9 • Decode • Do nothing • Execute • Determine whether to take branch based on jump condition and condition codes Taken • Memory • Do nothing • Write back jmp 7 0 jle 7 1 jl 7 2 je 7 3 jne 7 4 jge 7 5 jg 7 6 • Do nothing • PC Update • Set PC to Dest if branch taken or to incremented PC if not branch if MEM[PC]== jmp Dest if (cond) PC Dest else PC + 9 52

Stage Computation: Jumps Fetch j. XX Dest icode: ifun M 1[PC] Read instruction byte

Stage Computation: Jumps Fetch j. XX Dest icode: ifun M 1[PC] Read instruction byte val. C M 8[PC+1] val. P PC+9 Read destination address Fall through address Cnd Cond(CC, ifun) Take branch? PC Cnd ? val. C : val. P Update PC Decode Execute Memory Write back PC update • Compute both addresses • Choose based on setting of condition codes and branch condition if MEM[PC]== jmp Dest if (cond) PC Dest else PC + 9 53

Jump D Reg Write val. B r. B M U X P C Instr

Jump D Reg Write val. B r. B M U X P C Instr Addr Instruction Mem r. B M U r. A X r. A Dest. E Val. E M ALU U OP X 0 M U X Val. A Register file Mem Write A L U Read Data Address Write Data Mem MEM WB PC D 2 10 9 M U X A DD if MEM[PC]== jmp Dest PC Dest M U X From ALU From Mem MUX Select IF ID EX Combinational state update logic 54

Unconditional Jump D Reg Write val. B r. B M U X P C

Unconditional Jump D Reg Write val. B r. B M U X P C Instr Addr Instruction Mem r. B M U r. A X r. A Dest. E Val. E M ALU U OP X 0 M U X Val. A Register file Mem Write A L U Read Data Address Write Data Mem MEM WB PC D 2 10 9 M U X A DD if MEM[PC]== jmp Dest PC Dest M U X From ALU From Mem MUX Select IF ID EX Combinational state update logic 55

Conditional Jump D Reg Write val. B r. B M U X P C

Conditional Jump D Reg Write val. B r. B M U X P C Instr Addr Instruction Mem r. B M U r. A X r. A Dest. E Val. E M ALU U OP X 0 M U X Val. A Register file Mem Write A L U Read Data Address Write Data Mem MEM WB PC D 2 10 9 M U X A DD if MEM[PC]== jmp Dest if (cond) PC Dest else PC + 9 M U X From ALU From Mem MUX Select IF ID EX Combinational state update logic 56

Executing call Dest 8 0 Dest return: XX XX target: XX XX • Fetch

Executing call Dest 8 0 Dest return: XX XX target: XX XX • Fetch • Read 9 bytes • Increment PC by 9 • Decode • Read stack pointer • Execute • Decrement stack pointer by 8 • Memory • Write incremented PC to new value of stack pointer • Write back • Update stack pointer • PC Update • Set PC to Dest if MEM[PC]== call Dest MEM [R[rsp]-8] PC + 9 R[rsp] - 8 PC Dest 57

Stage Computation: call Dest icode: ifun M 1[PC] Read instruction byte val. C M

Stage Computation: call Dest icode: ifun M 1[PC] Read instruction byte val. C M 8[PC+1] val. P PC+9 Read destination address Compute return point val. B R[%rsp] val. E val. B + – 8 Read stack pointer Decrement stack pointer Memory Write M 8[val. E] val. P R[%rsp] val. E Write return value on stack Update stack pointer back PC update PC val. C Set PC to destination Fetch Decode Execute • Use ALU to decrement stack pointer • Store incremented PC if MEM[PC]== call Dest MEM [R[rsp]-8] PC + 9 R[rsp] - 8 PC Dest 58

Call D r. B M U X 2 10 9 P C Instr Addr

Call D r. B M U X 2 10 9 P C Instr Addr Instruction Mem M U X A DD if MEM[PC]== call Dest MEM [R[rsp]-8] PC + 9 R[rsp] - 8 PC Dest rsp r. B M U X M r. A U rsp X D Reg Write val. B r. A Dest. E Val. E M ALU U OP X 0 Val. A Register file M U X 8 Mem Write A L U Read Data Address M U X Data Mem Write Data From ALU From Mem MUX Select From PC + x IF ID EX MEM WB Combinational state update logic PC 59

Call: Decrement stack pointer D r. B M U X 2 10 9 P

Call: Decrement stack pointer D r. B M U X 2 10 9 P C Instr Addr Instruction Mem M U X A DD if MEM[PC]== call Dest MEM [R[rsp]-8] PC + 9 R[rsp] - 8 PC Dest rsp r. B M U X M r. A U rsp X D Reg Write val. B r. A Dest. E Val. E M ALU U OP X 0 Val. A Register file M U X 8 Mem Write A L U Read Data Address M U X Data Mem Write Data From ALU From Mem MUX Select From PC + x IF ID EX MEM WB Combinational state update logic PC 60

Call: Write return address to memory D r. B M U X 2 10

Call: Write return address to memory D r. B M U X 2 10 9 P C Instr Addr Instruction Mem M U X A DD if MEM[PC]== call Dest MEM [R[rsp]-8] PC + 9 R[rsp] - 8 PC Dest rsp r. B M U X M r. A U rsp X D Reg Write val. B r. A Dest. E Val. E M ALU U OP X 0 Val. A Register file M U X 8 Mem Write A L U Read Data Address M U X Data Mem Write Data From ALU From Mem MUX Select From PC + x IF ID EX MEM WB Combinational state update logic PC 61

Call: Update rsp in the register file D r. B M U X 2

Call: Update rsp in the register file D r. B M U X 2 10 9 P C Instr Addr Instruction Mem M U X A DD if MEM[PC]== call Dest MEM [R[rsp]-8] PC + 9 R[rsp] - 8 PC Dest rsp r. B M U X M r. A U rsp X D Reg Write val. B r. A Dest. E Val. E M ALU U OP X 0 Val. A Register file M U X 8 Mem Write A L U Read Data Address M U X Data Mem Write Data From ALU From Mem MUX Select From PC + x IF ID EX MEM WB Combinational state update logic PC 62

Call: Update PC D r. B M U X 2 10 9 P C

Call: Update PC D r. B M U X 2 10 9 P C Instr Addr Instruction Mem M U X A DD if MEM[PC]== call Dest MEM [R[rsp]-8] PC + 9 R[rsp] - 8 PC Dest rsp r. B M U X M r. A U rsp X D Reg Write val. B r. A Dest. E Val. E M ALU U OP X 0 Val. A Register file M U X 8 Mem Write A L U Read Data Address M U X Data Mem Write Data From ALU From Mem MUX Select From PC + x IF ID EX MEM WB Combinational state update logic PC 63

Executing ret 9 0 return: • Fetch • Read 1 byte • Decode •

Executing ret 9 0 return: • Fetch • Read 1 byte • Decode • Read stack pointer • Execute • Increment stack pointer by 8 XX XX • Memory • Read return address from old stack pointer • Write back • Update stack pointer • PC Update • Set PC to return address if MEM[PC]== ret PC MEM [R[rsp]] R[rsp] + 8 64

Stage Computation: ret icode: ifun M 1[PC] Read instruction byte val. A R[%rsp] val.

Stage Computation: ret icode: ifun M 1[PC] Read instruction byte val. A R[%rsp] val. B R[%rsp] val. E val. B + 8 Read operand stack pointer Increment stack pointer Memory Write val. M M 8[val. A] R[%rsp] val. E Read return address Update stack pointer back PC update PC val. M Set PC to return address Fetch Decode Execute • Use ALU to increment stack pointer • Read return address from memory if MEM[PC]== ret PC MEM [R[rsp]] R[rsp] + 8 65

Ret D r. B M U X 2 10 9 P C Instr Addr

Ret D r. B M U X 2 10 9 P C Instr Addr Instruction Mem M U X A DD if MEM[PC]== ret PC MEM [R[rsp]] R[rsp] + 8 rsp r. B M U X M r. A U rsp X D Reg Write val. B r. A Dest. E Val. E M ALU U OP X 0 Val. A Register file M U X 8 Mem Write M U X A L U M U X Address Data Mem Write Data Read Data From ALU From Mem MUX Select From PC + x IF ID EX MEM WB Combinational state update logic PC 66

Ret: Increment stack pointer D r. B M U X 2 10 9 P

Ret: Increment stack pointer D r. B M U X 2 10 9 P C Instr Addr Instruction Mem M U X A DD if MEM[PC]== ret PC MEM [R[rsp]] R[rsp] + 8 rsp r. B M U X M r. A U rsp X D Reg Write val. B r. A Dest. E Val. E M ALU U OP X 0 Val. A Register file M U X 8 Mem Write M U X A L U M U X Address Data Mem Write Data Read Data From ALU From Mem MUX Select From PC + x IF ID EX MEM WB Combinational state update logic PC 67

Ret: Read return address from Memory D r. B M U X 2 10

Ret: Read return address from Memory D r. B M U X 2 10 9 P C Instr Addr Instruction Mem M U X A DD if MEM[PC]== ret PC MEM [R[rsp]] R[rsp] + 8 rsp r. B M U X M r. A U rsp X D Reg Write val. B r. A Dest. E Val. E M ALU U OP X 0 Val. A Register file M U X 8 Mem Write M U X A L U M U X Address Data Mem Write Data Read Data From ALU From Mem MUX Select From PC + x IF ID EX MEM WB Combinational state update logic PC 68

Ret: Update PC D r. B M U X 2 10 9 P C

Ret: Update PC D r. B M U X 2 10 9 P C Instr Addr Instruction Mem M U X A DD if MEM[PC]== ret PC MEM [R[rsp]] R[rsp] + 8 rsp r. B M U X M r. A U rsp X D Reg Write val. B r. A Dest. E Val. E M ALU U OP X 0 Val. A Register file M U X 8 Mem Write M U X A L U M U X Address Data Mem Write Data Read Data From ALU From Mem MUX Select From PC + x IF ID EX MEM WB Combinational state update logic PC 69

Ret: Update rsp D r. B M U X 2 10 9 P C

Ret: Update rsp D r. B M U X 2 10 9 P C Instr Addr Instruction Mem M U X A DD if MEM[PC]== ret PC MEM [R[rsp]] R[rsp] + 8 rsp r. B M U X M r. A U rsp X D Reg Write val. B r. A Dest. E Val. E M ALU U OP X 0 Val. A Register file M U X 8 Mem Write M U X A L U M U X Address Data Mem Write Data Read Data From ALU From Mem MUX Select From PC + x IF ID EX MEM WB Combinational state update logic PC 70

Single-Cycle Datapath for Stack Operations

Single-Cycle Datapath for Stack Operations

Executing popq r. A • Fetch • Read 2 bytes • Decode • Read

Executing popq r. A • Fetch • Read 2 bytes • Decode • Read stack pointer • Execute • Increment stack pointer by 8 b 0 r. A 8 • Memory • Read from old stack pointer • Write back • Update stack pointer • Write result to register • PC Update • Increment PC by 2 if MEM[PC]== pop R[r. A] MEM [R[rsp]] R[rsp] + 8 72

Stage Computation: popq r. A Fetch Decode Execute icode: ifun M 1[PC] r. A:

Stage Computation: popq r. A Fetch Decode Execute icode: ifun M 1[PC] r. A: r. B M 1[PC+1] Read instruction byte Read register byte val. P PC+2 val. A R[%rsp] val. B R[%rsp] Compute next PC Read stack pointer Increment stack pointer val. E val. B + 8 Memory Write val. M M 8[val. A] R[%rsp] val. E back PC update R[r. A] val. M PC val. P Read from stack Update stack pointer Write back result Update PC • Use ALU to increment stack pointer • Must update two registers if MEM[PC]== pop • Popped value • New stack pointer R[r. A] MEM [R[rsp]] R[rsp] + 8 73

Pop D r. B M U X 2 10 9 P C Instr Addr

Pop D r. B M U X 2 10 9 P C Instr Addr Instruction Mem M U X A DD if MEM[PC]== pop R[r. A] MEM [R[rsp]] R[rsp] + 8 rsp r. B M U X M r. A U rsp X D Reg Write val. B r. A Dest. E Val. E M ALU U OP X 0 Val. A Register file M U X 8 Mem Write M U X A L U M U X Address Data Mem Write Data Read Data From ALU From Mem MUX Select From PC + x IF ID EX MEM WB Combinational state update logic PC 74

Pop D r. B M U X P C Instr Addr Instruction Mem rsp

Pop D r. B M U X P C Instr Addr Instruction Mem rsp r. B M U X M r. A U rsp X Reg Write val. B r. A Val. A Dest. E Register file Val. E Dest. M 2 10 9 M U X A DD D 0 8 M ALU U OP X M U X Val. M M U X Mem Write A L U M U X Address Write Data Mem Read Data From ALU From Mem MUX Select From PC + x 75

Pop: Increment stack pointer D r. B M U X P C Instr Addr

Pop: Increment stack pointer D r. B M U X P C Instr Addr Instruction Mem rsp r. B M U X M r. A U rsp X Reg Write val. B r. A Val. A Dest. E Register file Val. E Dest. M 2 10 9 M U X A DD D 0 8 M ALU U OP X M U X Val. M M U X Mem Write A L U M U X Address Write Data Mem Read Data From ALU From Mem MUX Select From PC + x if MEM[PC]== pop R[r. A] MEM [R[rsp]] 76 R[rsp] +8

Pop: Read pushed value from Memory D r. B M U X P C

Pop: Read pushed value from Memory D r. B M U X P C Instr Addr Instruction Mem rsp r. B M U X M r. A U rsp X Reg Write val. B r. A Val. A Dest. E Register file Val. E Dest. M 2 10 9 M U X A DD D 0 8 M ALU U OP X M U X Val. M M U X Mem Write A L U M U X Address Write Data Mem Read Data From ALU From Mem MUX Select From PC + x if MEM[PC]== pop R[r. A] MEM [R[rsp]] 77 R[rsp] +8

Pop: Move the value to register file D r. B M U X P

Pop: Move the value to register file D r. B M U X P C Instr Addr Instruction Mem rsp r. B M U X M r. A U rsp X Reg Write val. B r. A Val. A Dest. E Register file Val. E Dest. M 2 10 9 M U X A DD D 0 8 M ALU U OP X M U X Val. M M U X Mem Write A L U M U X Address Write Data Mem Read Data From ALU From Mem MUX Select From PC + x if MEM[PC]== pop R[r. A] MEM [R[rsp]] 78 R[rsp] +8

Pop: Writeback rsp value D r. B M U X P C Instr Addr

Pop: Writeback rsp value D r. B M U X P C Instr Addr Instruction Mem rsp r. B M U X M r. A U rsp X Reg Write val. B r. A Val. A Dest. E Register file Val. E Dest. M 2 10 9 M U X A DD D 0 8 M ALU U OP X M U X Val. M M U X Mem Write A L U M U X Address Write Data Mem Read Data From ALU From Mem MUX Select From PC + x if MEM[PC]== pop R[r. A] MEM [R[rsp]] 79 R[rsp] +8

Pop D r. B M U X P C Instr Addr Instruction Mem rsp

Pop D r. B M U X P C Instr Addr Instruction Mem rsp r. B M U X M r. A U rsp X Reg Write val. B r. A Val. A Dest. E Register file Val. E Dest. M 2 10 9 M U X A DD D 0 8 M ALU U OP X M U X Val. M M U X Mem Write A L U M U X Address Write Data Mem Read Data From ALU From Mem MUX Select From PC + x 80

Pop D r. B M U X P C Instr Addr Instruction Mem rsp

Pop D r. B M U X P C Instr Addr Instruction Mem rsp r. B M U X M r. A U rsp X Reg Write r. B r. A 2 10 9 M U X A DD D val. B Val. A Dest. E Register file Val. E Dest. M 0 8 M ALU U OP X M U X Val. M Mem Write A L U M U X Address Write Data Mem Read Data From ALU From Mem From PC + x 81

Evaluating the Single. Cycle Microarchitecture

Evaluating the Single. Cycle Microarchitecture

A Single-Cycle Microarchitecture • Is this a good idea/design? • When is this a

A Single-Cycle Microarchitecture • Is this a good idea/design? • When is this a good design? • When is this a bad design? • How can we design a better microarchitecture? 83

A Single-Cycle Microarchitecture: Analysis • Every instruction takes 1 cycle to execute • CPI

A Single-Cycle Microarchitecture: Analysis • Every instruction takes 1 cycle to execute • CPI (Cycles per instruction) is strictly 1 • How long each instruction takes is determined by how long the slowest instruction takes to execute • Even though many instructions do not need that long to execute • Clock cycle time of the microarchitecture is determined by how long it takes to complete the slowest instruction • Critical path of the design is determined by the processing time of the slowest instruction 84

What is the Slowest Instruction to Process? n n • • • Let’s go

What is the Slowest Instruction to Process? n n • • • Let’s go back to the basics All six phases of the instruction processing cycle take a single machine clock cycle to complete Fetch 1. Instruction fetch (IF) Decode 2. Instruction decode and Evaluate Address register operand fetch (ID/RF) Fetch Operands 3. Execute/Evaluate memory address (EX/AG) 4. Memory operand fetch (MEM) Execute 5. Store/writeback result (WB) Store Result • Do each of the above phases take the same time (latency) for all instructions? 85

Single-Cycle Datapath Analysis • Assume • • memory units (read or write): 200 ps

Single-Cycle Datapath Analysis • Assume • • memory units (read or write): 200 ps ALU and adders: 100 ps register file (read or write): 50 ps other combinational logic: 0 ps steps IF ID EX MEM mem WB RF Delay resources mem RF ALU Reg-Reg Op 200 50 100 50 400 ir mov 200 50 100 50 400 LW 200 50 100 200 50 600 SW 200 50 100 200 Call 200 50 100 200 Jump 200 550 50 600 200 86

Ld Datapath 250 ps 200 ps P C Instr Addr Instruction Mem 100 ps

Ld Datapath 250 ps 200 ps P C Instr Addr Instruction Mem 100 ps 10 r. A Dest. E Val. E 600 ALU OP val. B r. B M U r. A X 350 ps Reg Write A L U M U X Val. A Register psfile 550 ps Read Data Address Write Data Mem MEM WB PC D A DD if MEM[PC]== mrmovq Disp (r. B), r. A EA = Disp + R[r. B] R[r. A] MEM[EA] PC + 10 M U X From ALU From Mem MUX Select IF ID EX Combinational state update logic 87

Single Cycle u. Arch: Complexity • Contrived • All instructions run as slow as

Single Cycle u. Arch: Complexity • Contrived • All instructions run as slow as the slowest instruction • Inefficient • All instructions run as slow as the slowest instruction • Must provide worst-case combinational resources in parallel as required by any instruction • Need to replicate a resource if it is needed more than once by an instruction during different parts of the instruction processing cycle • Not necessarily the simplest way to implement an ISA • Single-cycle implementation of REP MOVS (x 86) or INDEX (VAX)? • Not easy to optimize/improve performance • Optimizing the common case does not work (e. g. common instructions) • Need to optimize the worst case all the time 88

(Micro)architecture Design Principles • Critical path design • Find and decrease the maximum combinational

(Micro)architecture Design Principles • Critical path design • Find and decrease the maximum combinational logic delay • Break a path into multiple cycles if it takes too long • Bread and butter (common case) design • Spend time and resources on where it matters most • i. e. , improve what the machine is really designed to do • Common case vs. uncommon case • Balanced design • Balance instruction/data flow through hardware components • Design to eliminate bottlenecks: balance the hardware for the work 89

Single-Cycle Design vs. Design Principles n. Critical path design n. Bread and butter (common

Single-Cycle Design vs. Design Principles n. Critical path design n. Bread and butter (common case) design n. Balanced design How does a single-cycle microarchitecture fare in light of these principles? 90

Intro to Microarchitecture: Single-Cycle CS 3330 Samira Khan University of Virginia Feb 14, 2017

Intro to Microarchitecture: Single-Cycle CS 3330 Samira Khan University of Virginia Feb 14, 2017

Stage Computation: Cond. Move Fetch cmov. XX r. A, r. B icode: ifun M

Stage Computation: Cond. Move Fetch cmov. XX r. A, r. B icode: ifun M 1[PC] r. A: r. B M 1[PC+1] Read instruction byte Read register byte val. P PC+2 val. A R[r. A] val. B 0 val. E val. B + val. A If ! Cond(CC, ifun) r. B 0 x. F Compute next PC Read operand A Memory Write R[r. B] val. E Write back result back PC update PC val. P Update PC Decode Execute Pass val. A through ALU (Disable register update) • Read register r. A and pass through ALU • Cancel move by setting destination register to 0 x. F • If condition codes & move condition indicate no move if MEM[PC]== cmov r. A, r. B if (cond) R[r. B] R[r. A] If (!cond) R[r. B] 0 x. F 92

D r. B M U X 2 10 9 P C Instr Addr Instruction

D r. B M U X 2 10 9 P C Instr Addr Instruction Mem M U X A DD if MEM[PC]== cmov r. A, r. B if (cond) R[r. B] R[r. A] If (!cond) R[r. B] 0 x. F rsp r. B M U X M r. A U rsp X D Reg Write val. B r. A Dest. E Val. E M ALU U OP X 0 Val. A Register file M U X 8 Mem Write M U X A L U M U X Address Data Mem Write Data Read Data From ALU From Mem MUX Select From PC + x IF ID EX MEM WB Combinational state update logic PC 93