Digital Logic Design Dr Waseem Ikram Lecture 06

Digital Logic & Design Dr. Waseem Ikram Lecture 06

Recap n n n Logic Gates Basic Building Blocks Symbol Performs unique function Represented by a function/truth table Function expression Timing Diagram

Recap n n n AND Gate F=A. B OR Gate F=A+B NOT Gate AND Gate enables/disables device OR Gate car door alarm system NOT Gate 1’s complement

Recap n n n n Alternate Symbolic representations NAND Gate NOT-AND operation Universal NAND Gate NOR Gate NOT-OR operation Universal NOR Gate

NOR Universal Gate Input A 0 0 1 1 B 0 1 Output F 0 1 1 1

NOR Universal Gate Input A 0 0 1 1 B 0 1 Output F 0 0 0 1

NAND-NOR Universal Gate

NAND Gate Applications n Device Failure Alarm

NOR Gate Applications n Washing Machine Controller

XOR Gate n n n 1 output 2 inputs Multiple inputs

XOR Gate function Input A 0 0 1 1 B 0 1 Output F 0 1 1 0

XOR Gate Timing Diagram

XNOR Gate n n n 1 output 2 inputs Multiple inputs

XNOR Gate function Input A 0 0 1 1 B 0 1 Output F 1 0 0 1

XNOR Gate Timing Diagram

XOR Gate Applications n Detecting odd number of 1’s

XNOR Gate Applications n Detecting even number of 1’s

TTL/CMOS NOT Gate +VCC +V Vi/p P-Type MOSFET Vo/p NPN Transistor +VDD Vi/p N-Type MOSFET Vo/p

Type of IC Logic Gates n n n n 74 XX 00 74 XX 02 74 XX 04 74 XX 08 74 XX 10 74 XX 11 74 XX 20 Quad 2 -input NAND Gate Quad 2 -input NOR Gate Hex Inverter Quad 2 -input AND Gate Triple 3 -input NAND Gate Triple 3 -input AND Gate Dual 4 -input NAND Gate

Type of IC Logic Gates n n n 74 XX 21 Dual 2 -input AND Gate 74 XX 27 Triple 3 -input NOR Gate 74 XX 30 Single 8 -input NAND Gate 74 XX 32 Quad 2 -input OR Gate 74 XX 86 Quad 2 -input XOR Gate 74 XX 133 Single 13 -input NAND Gate

Logic Gate Integrated Circuits

Logic Gate Integrated Circuits

Integrated Circuits (IC) n n n CMOS Complementary Metal Oxide Logic TTL Transistor-Transistor Logic ECL Emitter Coupled Logic PMOS p-channel MOS transistor NMOS n-channel MOS transistor E 2 CMOS

Operational Characteristics n n n DC Supply Voltage Noise Margin Power Dissipation Frequency Response Fan Out