Digital Logic Design Dr Waseem Ikram Lecture No

Digital Logic & Design Dr. Waseem Ikram Lecture No. 28

Synchronous Decade Counter

Timing diagram of a Synchronous Decade Counter

74 HC 163 4 -bit Synchronous Counter

Timing diagram of the 74 HC 163 Synchronous counter

Cascaded Decade Counters

Timing diagram of a Cascaded Decade Counter

74 HC 163 configured as Mod-7 counter

The timing diagram of a truncated Mod-7 Counter

74 HC 161 configured as Mod-9 counter

Timing diagram of a 74 HC 161 configured as Mod-9 counter

74 HC 163 counters connected for cascaded truncated count sequence

Up-counting sequence of a 3 -bit Synchronous Counter Clock Pulse Q 2 Q 1 Q 0 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1

Down-counting sequence of a 3 -bit Synchronous Counter Clock Q 2 Pulse Q 1 Q 0 0 1 1 1 0 2 1 0 1 3 1 0 0 4 0 1 1 5 0 1 0 6 0 0 1 7 0 0 0

Recap n n Down Counters Synchronous Counter n n n 3 -bit counter 4 -bit counter Synchronous Decade Counter

Synchronous Counter n n Decade Counter timing diagram (fig 1) Mod-n Synchronous Counter IC 74 HC 163 Mod-16 Counter (fig 2) IC 74 HC 160 Mod-10 Counter

Cascading & Truncated Sequence Counters n n Cascading Counters (fig 3) IC counters with truncated seq. (fig 4) IC 74 x 161 counter with Asyn. Clear (fig 5) Cascading counters with truncated sequence (fig 6)

Up-Down Counters n Up-Down Counter (tab 1)