Digital Logic Design Dr Waseem Ikram Lecture No

Digital Logic & Design Dr. Waseem Ikram Lecture No. 25

J-K flip-flop with Asynchronous Preset and Clear inputs

Logic Symbol of a J-K flip-flop with Asynchronous inputs

Truth table of J-K flip-flop with Asynchronous inputs Input Output PRE Qt+1 CLR 0 0 Invalid 0 1 1 1 0 0 1 1 Clocked operation

Timing diagram of a J-K flip-flop with Preset and Clear inputs

Master-Slave flip-flop

Truth table of the Master-Slave JK flip-flop Input CL K Ou tpu t J K Qt+ 1 Pul 0 se 0 Qt Pul 0 se 1 0 Pul 1 se 0 1 Pul 1 1 Qt

Timing diagram of a Master Slave J-K flipflop

Propagation Delay, clock to low-to-high transition of the output

Propagation Delay, clock to highto-low transition of the output

Propagation Delay, preset to low-to -high transition of the output

Set-up time for a D flip-flop

Propagation Delay, clear to high-to-low transition of the output

Hold time for a D flip-flop

Circuit diagram of a One-Shot

Timing diagram of a One-Shot

Timing diagram of a non retriggerable One-Shot Trigger Output of One-Shot t 1 t 2 t 3 t 4 t 5 t 6

Timing diagram of a nonretriggerable One-Shot with ignored triggers Trigger Output of One-Shot t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10

Recap n D flip-flop applications n n n Data Storage Synchronizing Asynchronous Inputs Parallel data Transfer J-K flip-flop applications n n Sequence Detector Frequency Divider Shift Register Counter

Asynchronous Inputs n n J-K flip-flop with asynch. inputs (fig 1 a) Logic symbol asynch. J-K flip-flop (fig 1 b) Function table (tab 1) Timing diagram (fig 1 c)

Master-Slave flip-flop n Master Slave flip-flop (fig 2 a) n n Function table (tab 2) Timing diagram (fig 2 b)

Operating Conditions n Flip-Flop Operating Conditions n n n Propagation delay (fig 3, 4, 5, 6) Set-up time (fig 7) Hold Time (fig 8) Max clock frequency Pulse Width Power Dissipation

Multivibrators n Mono-Stable Multi-vibrator (fig 9) n n Non-Retriggerable (fig 10) Retriggerable (fig 11)