Digital Logic Design Dr Waseem Ikram Lecture 40

Digital Logic & Design Dr. Waseem Ikram Lecture 40

Memory array decoded by Row and Columns Decoders

Input/Output Data Circuit

Timing diagram of a Read Cycle

Timing diagram of a Write Cycle

Block diagram of a Synchronous Burst RAM

Burst Logic Circuit

Writing a 1 or 0 into the DRAM cell

Reading a 0 or 1 from the DRAM cell

Refreshing a DRAM cell

Circuit Diagram of a 1 M x 1 DRAM Refresh Control and Timing Refresh Counter Row Decoder Address Lines A 0 -A 9 Memory Array 1024 rows x 1024 columns Row Address Latch Data Selector Input/Output Buffers and Sense Amplifiers Column Address Latch RAS CAS D OUT DIN Column Decoder R/W E

Recap n n n Memory n Latches and Flip-flops (small memory) n Computer Program Memory (large memory) Data Storage n Bits, Nibbles, Bytes, Words Memory Storage n Storage array of cells (stores 0 or 1) n Two dimensional array row & column

Recap n n n Memory Organization n Byte, Nibble, Bit Memory Capacity and Density Memory Block diagram and Signals n Address, Data, R/W and CS

Recap n n n Static RAM cell implementation Internal structure of 8 x 4 RAM 16 K x 8 RAM chip

Memory n n Row and column decoders in RAM (fig 1) Input/Output RAM circuit (fig 2) Read Cycle (fig 3) Write Cycle (fig 4)

Sync. Burst SRAM & DRAM n n Sync. Burst SRAM (fig 5) n Flow through SRAM n Pipelined SRAM Burst Logic Circuitry (fig 6) DRAM Structure (fig 7 a) n Writing to DRAM (fig 7 a) n Reading from DRAM (fig 7 b) n Refreshing DRAM (fig 7 c) Address Multiplexing (fig 8)