Wireless Metrology and Process Control for Semiconductor Manufacturing

Wireless Metrology and Process Control for Semiconductor Manufacturing Kameshwar Poolla Mechanical Engineering Electrical Engineering & CS University of California, Berkeley This research was supported by NSF, UC SMART, & gifts from Intel, AMD, Novellus, Applied Materials, Cypress, Lam Research, TEL, Nikon. April 10, 2006

semiconductor manufacturing background 12/17/2021 2

What is it? • Selective deposition & selective removal of various materials to form ICs • Selectivity is done by protecting desired areas with resist IBM Power PC 750 3 12/17/2021

Lithography • Expose Post Start Spin-coat Cr Mask Exposure with a. Resist Si wafer Bake Develop Etch or Deposit 4 12/17/2021

Process Overview Photomask Scanner PEB PAB Etch Resist Develop Track 5 12/17/2021 PDB Production Wafer Flow

Critical Dimension (CD) • Captures quality of pattern transfer • CD Target – desired width of printed lines • CD(x, y) – actual width of printed lines • Depends on (x, y) because process varies across wafer • Measured on test wafers using CD SEM or Scatterometry 6 12/17/2021

CD means μ and spreads σ • Want CD Mean at Target • small CD means faster switching speeds • CD spread Across wafer & wafer-to-wafer • small CD spread can use aggressive design rules higher device density better binning yields 7 12/17/2021

Bad Good 8 12/17/2021

Binning 11 nm Typical CD Distribution Target CD 6 nm Post On. Wafer Optimization Device/Fab Economics Bin 1 Bin 2 Bin 3 Intel P 4 Prices: $ Yield Improved Yield & Bin Sort = $$$ 9 12/17/2021 3. 8 GHz - $429 3. 2 GHz - $336 2. 8 GHz - $279

Post Exposure Bake • • Key step – greatly influences CD μ and Makes exposed resist diffuse To reduce standing wave patterns Gives better pattern transfer • Must be very accurately controlled • State-of-the-art ± 0. 3 ºC across 300 mm wafer 10 12/17/2021

PEB reduces Standing Waves 11 12/17/2021 Courtesy of CNF, Cornell University

Our Plan ~1997 • Decided to do Control of Lithography • Feedback Control requires Sensors & Actuators • Available Actuation? Plenty – exposure dose, focal plane, PEB Temp • Available Sensors in Lithography? Not many and pretty useless for control 12 12/17/2021

Need in situ Sensing wafers to be processed processing equipment finished wafer What was the state of the wafer during processing? 13 12/17/2021

in situ Sensing • Need wafer-state information – – Temperature in post-exposure bake Latent image in lithographic exposure Etch rate of wafer in plasma etch Deposition rate in CVD processes • The Big Problems – Chamber access – Deployment cost 14 12/17/2021

Solution: Sensor. Wafers In-situ sensor array with integrated power and telemetry 15 12/17/2021

The Approach processing equipment Sensor. Wafer data feedback process control wafers to be processed 16 12/17/2021 base station

Temperature Sensors • Useful for PEB, plasma etch, implant • Objectives Monitor wafer temperature at 4 locations (within 1ºC) • Design – – Off-the-shelf temperature sensor modules PIC microprocessor (with integrated 4 channel A/D) Infrared data transfer (Ir. DA compliant) Error detection (CRC-16) 17 12/17/2021

Early attempts … Batteries P P Ir-LED Sensor Ir-LED Problems: clearance, isolation, contamination & they are ugly ! 18 12/17/2021

Etch Rate Sensor • Sensor to measure polysilicon etch rate • Based on van der Pauw probe electrical filmthickness measurement: I I Poly-Si V 19 12/17/2021

Design # 1 20 12/17/2021

The effect of Temperature 21 12/17/2021

Results Problems: clearance, isolation, contamination 22 12/17/2021

Thermal Flux Sensors • Plasma etch is highly sensitive to wafer temp etch rate, selectivity, and anisotropy • Heat delivered to the wafer has two sources – Ion flux bombardment Indirect measure of physical etch – Exothermic chemical etch reactions Indirect measure of chemical etch • Want to resolve these heat fluxes – Can deduce sidewall, anisotropy etc. 23 12/17/2021

Heat flux sensor design • Simple, layered heat flux gauge • Not enough sensitivity Incident heat flux (q ) t 24 12/17/2021 Dielectric, thermal conductivity Temperature Sensors

Make the Heat Travel Far Incident heat flux Antenna 25 12/17/2021 Antenna Base Membrane T

Antenna / Membrane Structure Membrane Top View T D Heat flow within dielectric membrane b Heat sink 26 12/17/2021 Incident heat Heat flow T Heat sink Membrane Side View

Heat Flux Resolution • Discrimination between physical and chemical sources • Use two heat flux sensors: one exposed, one covered – Exposed sensor is heated by both sources – Covered sensor receives only physical heating 27 12/17/2021

Design #1 • • • Membrane: Silicon nitride Antenna: Si. O 2 / Aluminum Plasma-etched material: resist (O 2 plasma) Temperature sensors: polysilicon Tethered power and communication PR Al Si. O 2 Heat sink Si 28 12/17/2021 poly Si 3 N 4

Layout – Wheatstone Bridge Etched Sensor 29 12/17/2021 Non-Etched

Layout – Full Die (20 per wafer) Sensors Edgeboard Connector 30 12/17/2021

Design # 2 • Antenna: Undoped polysilicon (low ) • Linewidths: increased • Tethered power and communication PR poly Heat sink Si 31 12/17/2021 poly Si 3 N 4

Final Design 32 12/17/2021

Testing • Test sensors on the “bench” – Use an off-the-shelf heat flux sensor and a heating element to compare readings: heater sensor off-the-shelf sensor Aluminum heat sink vacuum chamber 33 12/17/2021

Bench-top Results 34 12/17/2021

Going up the food chain • Sensors become rapidly commodified • Value is in using the data • This is through Control, Modeling, Optimization • Examples – Equipment Control – Fault Detection and Isolation – Process Optimization 35 12/17/2021

The Value of Control • • • PEB Example Control spatial temperature of bake plate Yesterday ± 0. 3 °C Today ± 0. 15 °C Result: 1 nm reduction in CD spread Benefit: mid-sized fab in 1 st year of product lifecycle ~$3/die * 200 die/wafer * 20, 000 wafer/mon * 12 mon/yr • 144 M$ per year !! 36 12/17/2021