Semiconductor Manufacturing Technology Semiconductor Manufacturing Processes Conrad T

Semiconductor Manufacturing Technology: Semiconductor Manufacturing Processes Conrad T. Sorenson Praxair, Inc. 1999 Arizona Board of Regents for The University of Arizona NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing 1

Semiconductor Manufacturing Processes • • • Design Wafer Preparation Front-end Processes Photolithography Etch Cleaning Thin Films Ion Implantation Planarization Test and Assembly Wafer Preparation Design Thin Films Front-End Processes Photolithography Ion Implantation Etch Cleaning Planarization Test & Assembly NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing 2

Design • • • Establish Design Rules Circuit Element Design Interconnect Routing Device Simulation Pattern Preparation Wafer Preparation Design Thin Films Front-End Processes Photolithography Ion Implantation Etch Cleaning Planarization Test & Assembly NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing 3

Pattern Preparation Reticle Chrome Pattern Pellicle Quartz Substrate NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing 4

Wafer Preparation • • Polysilicon Refining Crystal Pulling Wafer Slicing & Polishing Epitaxial Silicon Deposition Wafer Preparation Design Thin Films Front-End Processes Photolithography Ion Implantation Etch Cleaning Planarization Test & Assembly NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing 5

Polysilicon Refining Chemical Reactions Silicon Refining: Si. O 2 + 2 C Si + 2 CO Silicon Purification: Si + 3 HCl HSi. Cl 3 + H 2 Silicon Deposition: HSi. Cl 3 + H 2 Si + 3 HCl Reactants H 2 Silicon Intermediates H 2 Si. Cl 2 HSi. Cl 3 NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing 6

Crystal Pulling Quartz Tube Rotating Chuck Process Conditions Flow Rate: 20 to 50 liters/min Time: 18 to 24 hours Temperature: >1, 300 degrees C Pressure: 20 Torr Materials Polysilicon Nodules * Ar * H 2 Seed Crystal Growing Crystal (boule) RF or Resistance Heating Coils Molten Silicon (Melt) Crucible * High proportion of the total product use NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing 7

Wafer Slicing & Polishing silicon wafer p+ silicon substrate The silicon ingot is sliced into individual wafers, polished, and cleaned. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing 3/15/98 PRAX 01 C. PPT Rev. 1. 0 8

Epitaxial Silicon Deposition silicon wafer Susceptor p- silicon epi layer Gas Input p+ silicon substrate Lamp Module Chemical Reactions Silicon Deposition: HSi. Cl 3 + H 2 Si + 3 HCl Process Conditions Flow Rates: 5 to 50 liters/min Temperature: 900 to 1, 100 degrees C. Pressure: 100 Torr to Atmospheric Silicon Sources Si. H 4 H 2 Si. Cl 2 HSi. Cl 3 * Si. Cl 4 * Dopants As. H 3 B 2 H 6 PH 3 Etchant HCl Carriers Ar H 2 * N 2 Quartz Lamps Wafers Exhaust * High proportion of the total product use NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing 9

Front-End Processes • Thermal Oxidation • Silicon Nitride Deposition - Low Pressure Chemical Vapor Deposition (LPCVD) • Polysilicon Deposition - Low Pressure Chemical Vapor Deposition (LPCVD) • Annealing Wafer Preparation Design Thin Films Front-End Processes Photolithography Ion Implantation Etch Cleaning Planarization Test & Assembly NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing 10

Front-End Processes Vertical LPCVD Furnace Exhaust Via Vacuum Pumps and Scrubber Chemical Reactions Thermal Oxidation: Si + O 2 Si. O 2 Nitride Deposition: 3 Si. H 4 + 4 NH 3 Si 3 N 4 + 12 H 2 Polysilicon Deposition: Si. H 4 Si + 2 H 2 Process Conditions (Silicon Nitride LPCVD) Flow Rates: 10 - 300 sccm Temperature: 600 degrees C. Pressure: 100 m. Torr Oxidation Polysilicon Nitride Annealing Quartz Tube 3 Zone Temperature Control Ar H 2 NH 3 * Ar N 2 H 2 Si. Cl 2 * He H 2 O Si. H 4 * N 2 H 2 Gas Inlet Cl 2 As. H 3 Si. H 4 * N 2 H 2 B 2 H 6 Si. Cl 4 HCl * PH 3 * High proportion of the total product use O 2 * 11 Dichloroethene * NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing

Photolithography • Photoresist Coating Processes • Exposure Processes Wafer Preparation Design Thin Films Front-End Processes Photolithography Ion Implantation Etch Cleaning Planarization Test & Assembly NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing 12

Photoresist Coating Processes photoresist field oxide p- epi p+ substrate Photoresists Negative Photoresist * Positive Photoresist * Other Ancillary Materials (Liquids) Edge Bead Removers * Anti-Reflective Coatings * Adhesion Promoters/Primers (HMDS) * Rinsers/Thinners/Corrosion Inhibitors * Contrast Enhancement Materials * Developers TMAH * Specialty Developers * Inert Gases Ar N 2 NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing 13

Exposure Processes photoresist field oxide p- epi p+ substrate Expose Kr + F 2 (gas) * Inert Gases N 2 NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing 14

Ion Implantation • Well Implants • Channel Implants • Source/Drain Implants Wafer Preparation Design Thin Films Front-End Processes Photolithography Ion Implantation Etch Cleaning Planarization Test & Assembly NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing 15

Ion Implantation Focus Beam trap and gate plate Neutral beam and beam path gated junction depth Neutral beam trap and beam gate Process Conditions Flow Rate: 5 sccm Pressure: 10 -5 Torr Accelerating Voltage: 5 to 200 ke. V Gases Ar As. H 3 B 11 F 3 * He N 2 PH 3 Si. H 4 Si. F 4 Ge. H 4 Resolving Aperture Y - axis scanner X - axis scanner Wafer in wafer process chamber Equipment Ground 180 k. V Solids Ga In Sb Liquids Al(CH 3)3 Acceleration Tube 90° Analyzing Magnet Terminal Ground Ion Source 20 k. V * High proportion of the total product use NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing 16

Etch • Conductor Etch - Poly Etch and Silicon Trench Etch - Metal Etch • Dielectric Etch Wafer Preparation Design Thin Films Front-End Processes Photolithography Ion Implantation Etch Cleaning Planarization Test & Assembly NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing 17

Conductor Etch Cluster Tool Configuration Wafers Chemical Reactions Silicon Etch: Si + 4 HBr Si. Br 4 + 2 H 2 Aluminum Etch: Al + 2 Cl 2 Al. Cl 4 Process Conditions Flow Rates: 100 to 300 sccm Pressure: 10 to 500 m. Torr RF Power: 50 to 100 Watts Polysilicon Etches HBr * C 2 F 6 SF 6 * NF 3 * O 2 Aluminum Etches Etch Chambers Transfer Chamber Loadlock RIE Chamber Transfer Chamber Gas Inlet Wafer RF Power BCl 3 * Cl 2 Diluents Ar He N 2 Exhaust * High proportion of the total product use NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing 18

Dielectric Etch Contact locations Cluster Tool Configuration Wafers Chemical Reactions Oxide Etch: Si. O 2 + C 2 F 6 Si. F 4 + CO 2 + CF 4 + 2 CO Process Conditions Flow Rates: 10 to 300 sccm Pressure: 5 to 10 m. Torr RF Power: 100 to 200 Watts Plasma Dielectric Etches CHF 3 * CF 4 C 2 F 6 C 3 F 8 CO * CO 2 SF 6 Si. F 4 Diluents Ar He N 2 Etch Chambers Transfer Chamber Loadlock RIE Chamber Transfer Chamber Gas Inlet Wafer RF Power Exhaust * High proportion of the total product use NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing 19

Cleaning • Critical Cleaning • Photoresist Strips • Pre-Deposition Cleans Wafer Preparation Design Thin Films Front-End Processes Photolithography Ion Implantation Etch Cleaning Planarization Test & Assembly NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing 20

Critical Cleaning Contact locations Process Conditions Temperature: Piranha Strip is 180 degrees C. RCA Clean SC 1 Clean (H 2 O + NH 4 OH + H 2 O 2) * * SC 2 Clean (H 2 O + HCl + H 2 O 2) * Piranha Strip * H 2 SO 4 + H 2 O 2 * Nitride Strip H 3 PO 4 * Oxide Strip HF + H 2 O * Dry Strip N 2 O O 2 CF 4 + O 2 O 3 Solvent Cleans NMP Proprietary Amines (liquid) Dry Cleans HF O 2 Plasma Alcohol + O 3 NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing 21

Thin Films • Chemical Vapor Deposition (CVD) Dielectric • CVD Tungsten • Physical Vapor Deposition (PVD) • Chamber Cleaning Wafer Preparation Design Thin Films Front-End Processes Photolithography Ion Implantation Etch Cleaning Planarization Test & Assembly NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing 22

Chemical Vapor Deposition (CVD) Dielectric Metering Pump Inert Mixing Gas TEOS Source Chemical Reactions Si(OC 2 H 5)4 + 9 O 3 Si. O 2 + 5 CO + 3 CO 2 + 10 H 2 O Process Conditions (ILD) Flow Rate: 100 to 300 sccm Pressure: 50 Torr to Atmospheric Vaporizer Direct Liquid Injection LPCVD Chamber CVD Dielectric O 2 O 3 TEOS * TMP * Transfer Chamber Process Gas Inlet Wafer RF Power Exhaust * High proportion of the total product use NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing 23

Chemical Vapor Deposition (CVD) Tungsten Input Cassette Output Cassette Chemical Reactions WF 6 + 3 H 2 W + 6 HF Process Conditions Flow Rate: 100 to 300 sccm Pressure: 100 m. Torr Temperature: 400 degrees C. CVD Dielectric WF 6 * Ar H 2 N 2 Wafer Hander Wafers Multistation Sequential Deposition Chamber Water-cooled Showerheads Resistively Heated Pedestal * High proportion of the total product use NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing 24

Physical Vapor Deposition (PVD) Physical Vapor Deposition Chambers Cluster Tool Configuration Wafers Process Conditions Pressure: < 5 m. Torr Temperature: 200 degrees C. RF Power: Transfer Chamber Loadlock Reactive Gases PVD Chamber N Barrier Metals Si. H 4 Ar N 2 Ti PVD Targets * Transfer Chamber Argon & Nitrogen S N Cryo Pump e+ Wafer Backside DC Power He Cooling Supply (+) * High proportion of the total product use NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing 25

Chamber Cleaning Multistation Sequential Deposition Chamber Water-cooled Showerheads Resistively Heated Pedestal Chemical Reactions Oxide Etch: Si. O 2 + C 2 F 6 Si. F 4 + CO 2 + CF 4 + 2 CO Process Conditions Flow Rates: 10 to 300 sccm Pressure: 10 to 100 m. Torr RF Power: 100 to 200 Watts Chamber Cleaning C 2 F 6 * NF 3 Cl. F 3 Aluminum Surface Coating Process Material Residue Chamber Wall Cross-Section * High proportion of the total product use NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing 26

Planarization • Oxide Planarization • Metal Planarization Wafer Preparation Design Thin Films Front-End Processes Photolithography Ion Implantation Etch Cleaning Planarization Test & Assembly NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing 27

Chemical Mechanical Planarization (CMP) Platen Head Sweep Slide Polishing Head Load/Unload Station Process Conditions (Oxide) Flow: 250 to 1000 ml/min Wafer Handling Robot & I/O Particle Size: 100 to 250 nm Concentration: 10 to 15%, 10. 5 to 11. 3 p. H Process Conditions (Metal) Flow: 50 to 100 ml/min Wafer Particle Size: 180 to 280 nm Carrier Concentration: 3 to 7%, 4. 1 - 4. 4 p. H Backing (Carrier) Film CMP (Oxide) Polyurethane Pad Conditioner Abrasive Silica Slurry * KOH * NH 4 OH H 2 O Pad Conditioner Carousel Polishing Pad Slurry Delivery Wafer CMP (Metal) Platen Alumina * * High proportion of the total product use. Fe. NO 3 NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing 28

Test and Assembly • • Electrical Test Probe Die Cut and Assembly Die Attach and Wire Bonding Final Test Wafer Preparation Design Thin Films Front-End Processes Photolithography Ion Implantation Etch Cleaning Planarization Test & Assembly NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing 29

Electrical Test Probe bonding pad nitride Metal 2 p-well n-channel transistor p+ substrate Defective IC Individual integrated circuits are tested to distinguish good die from bad ones. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing 30

Die Cut and Assembly Good chips are attached to a lead frame package. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing 31

Die Attach and Wire Bonding lead frame gold wire bonding pad connecting pin NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing 32

Final Test Chips are electrically tested under varying environmental conditions. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing 33

References 1. 2. 3. 4. 5. 6. 7. 8. CMOS Process Flow in Wafer Fab, Semiconductor Manufacturing Technology, DRAFT, Austin Community College, January 2, 1997. Semiconductor Processing with MKS Instruments, Inc. Worthington, Eric. “New CMP architecture addresses key process issues, ” Solid State Technology, January 1996. Leskonic, Sharon. “Overview of CMP Processing, ” SEMATECH Presentation, 1996. Gwozdz, Peter. “Semiconductor Processing Technology” SEMI, 1997. CVD Tungsten, Novellus Sales Brochure, 7/96. Fullman Company website. “Fullman Company - The Semiconductor Manufacturing Process, ” http: //www. fullman. com/semiconductors/index. html, 1997. Barrett, Craig R. “From Sand to Silicon: Manufacturing an Integrated Circuit, ” Scientific American Special Issue: The Solid State Century, January 22, 1998. NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing 34