Outline for Today Announcements Groups if you havent

Outline for Today • Announcements – Groups - if you haven’t sent me email do it by Sunday Nov 21 at 8 pm! After that, I’ll assign the rest of you into groups. » On following directions: to me at carla@cs. duke. edu with the subject line: 110 groups S 07. I am filtering on that subject line, so if you don’t use that, you might be spam-filtered. – If you weren’t here last time, fill out who’s who questionnaire (doc format on the web page). » What I learned… – Plug for Soph. and Juniors to do undergrad research experiences CRA awards • Objective of Today’s Lecture: Review of computer architecture 1 CPS 110

Need CPS 104++: Almost Everything You Wanted to Know About Operating System’s Interaction with Architecture but were Afraid to Ask

Basic Storyline – Evolution of HW Support • Computing from the (purely) architectural point of view: instruction cycle, register state, DMA I/O, interrupts. • Introduce execution of user programs into the picture and we want to restrict user code from having direct access to (at least) I/O -> protected instructions, kernel/user modes, system calls. • Add sharing among multiple users -> memory protection, timers, instructions to assist synchronization, process abstraction. 3 CPS 110

The Big Picture • The Five Classic Components of a Computer Processor Input Memory Control Datapath Output Von Neumann machine 4 CPS 110

System Organization Processor interrupts Cache Memory Bus I/O Bridge I/O Bus Main Memory Disk Controller Disk Graphics Controller Graphics Network Interface Network 5 CPS 110

System Organization Processor interrupts Cache Memory Bus I/O Bridge I/O Bus Main Memory Disk Controller Disk Memory hierarchy Disk Graphics Controller Graphics Network Interface Network 6 CPS 110

System Organization Processor interrupts Cache Memory Bus I/O Bridge I/O Bus Main Memory Disk Controller Disk Graphics Controller Graphics Network Interface Network 7 CPS 110

What do we need to know about the Processor? • Size (# bits) of effective memory addresses that can be generated by the program and therefore, the amount of memory that can be accessed. • Information that is crucial process state or execution context describing the execution of a program (e. g. program counter, stack pointer). This is stuff that needs to be saved and restored on context switch. • When the execution cycle can be interrupted. What is an indivisible operation in given architecture? 8 CPS 110

A "Typical" RISC Processor • • 32 -bit fixed format instruction 32 (32, 64)-bit GPR (general purpose registers) Status registers (condition codes) Load/Store Architecture – Only accesses to memory are with load/store instructions – All other operations use registers – addressing mode: base register + 16 -bit offset • Not Intel x 86 architecture! 9 CPS 110

Example: MIPS Register-Register 31 26 25 Op 21 20 Rs 1 16 15 Rs 2 11 10 6 5 Rd 0 Opx Register-Immediate 31 26 25 Op 21 20 Rs 1 16 15 0 immediate Rd Branch, Load, Store 31 26 25 Op Rs 1 21 20 16 15 Rs 2/Opx 0 immediate Jump / Call 31 26 25 Op 0 target So, how many memory locations can we address? 10 Can we tell how much memory the machine has? CPS 110

Executing a Program • Thread of control (program counter) • Basic steps for program execution (execution cycle) – fetch instruction from Memory[PC], decode it – execute the instruction (fetching any operands, storing result, setting cond codes, etc. ) – increment PC (unless jump) 11 CPS 110

An Abstract View of the Implementation Clk Simplistic… PC Instruction Address Ideal Instruction Memory Instruction Rd Rs 5 5 Rt 5 Imm 16 A Clk Rw Ra Rb 32 64 -bit Registers 32 32 ALU 32 B 32 Data Address Data. In Ideal Data Memory Data. Out Clk 12 CPS 110

Program Stack • Well defined register is stack pointer • Stack is used for Frame 0 – passing parameters (function, method, procedure, subroutine) – storing local variables Frame 1 A stack frame (Activation Record) Return results Frame ptr Return Address Old frame ptr arg 1 arg 2 Frame 2 stack ptr Local variables First few return results and arguments can be mapped to specific registers (calling conventions) 13 CPS 110

What do we need to know about the Processor? 4 Size (# bits) of effective memory addresses that can be generated by the program and therefore, the amount of memory that can be accessed. 4 Information that is crucial process state or execution context describing the execution of a program (e. g. program counter, stack pointer). This is stuff that needs to be saved and restored on context switch. • When the execution cycle can be interrupted. What is an indivisible operation in given architecture? 14 CPS 110

Interrupts are a Key Mechanism

Role of Interrupts in I/O So, the program needs to access an I/O device… • Start an I/O operation (special instructions or memorymapped I/O) • Device controller performs the operation asynchronously (in parallel with) CPU processing (between controller's buffer & device). • If DMA, data transferred between controller's buffer and memory without CPU involvement. • Interrupt signals I/O completion when device is done. First instance of concurrency we’ve encountered I/O Overlap 16 CPS 110

Interrupts and Exceptions • Unnatural change in control flow • Interrupt is external event – devices: disk, network, keyboard, etc. – clock for timeslicing – These are useful events, must do something when they occur. • Exception is potential problem with program – – – segmentation fault bus error divide by 0 Don’t want my bug to crash the entire machine page fault (virtual memory…) 17 CPS 110

CPU handles interrupt – CPU stops current operation*, saves current program counter and other processor state ** needed to continue at interrupted instruction. – Accessing vector table, in memory, it jumps to address of appropriate interrupt service routine for this event. – Handler does what needs to be done. – Restores saved state at interrupted instruction * At what point in the execution cycle does this make sense? ** Need someplace to save it! Data structures in OS kernel. CPS 110 18

An Execution Context • The state of the CPU associated with a thread of control (process) – general purpose registers (integer and floating point) – status registers (e. g. , condition codes) – program counter, stack pointer • Need to be able to switch between contexts – better utilization of machine (overlap I/O of one process with computation of another) – timeslicing: sharing the machine among many processes – different modes (Kernel v. s. user) 19 CPS 110

Handling an Interrupt/Exception User Program ld add st mul beq ld sub bne Interrupt Handler RETT • Invoke specific kernel routine based on type of interrupt – interrupt/exception handler • Must determine what caused interrupt – could use software to examine each device – PC = interrupt_handler • Vectored Interrupts – PC = interrupt_table[i] – kernel initializes table at boot time • Clear the interrupt • May return from interrupt (RETT) to different process (e. g, context switch) 20 CPS 110

Context Switches • Save current execution context – Save registers and program counter – information about the context (e. g. , ready, blocked) • Restore other context • Need data structures in kernel to support this – process control block • Why do we context switch? – Timeslicing: HW clock tick – I/O begin and/or end • How do we know these events occur? – Interrupts. . . 21 CPS 110

Crossing Protection Boundaries • For a user to do something "privileged", it must invoke an OS procedure providing that service. How? • System Calls – special trap instruction that causes an exception which vectors to a kernel handler – parameters indicate which system routine called 22 CPS 110

A System Call User Program ld add st TA 6 beq ld sub bne Kernel Trap Handler RETT Service Routines • Special Instruction to change modes and invoke service – read/write I/O device – create new process • Invokes specific kernel routine based on argument • kernel defined interface • May return from trap to different process (e. g, context switch) • RETT, instruction to return to user process 23 CPS 110

User / Kernel Modes • Hardware support to differentiate between what we'll allow user code to do by itself (user mode) and what we'll have the OS do (kernel mode). • Mode indicated by status bit in protected processor register. • Privileged instructions can only be executed in kernel mode (I/O instructions). 24 CPS 110

Execution Mode • What if interrupt occurs while in interrupt handler? – Problem: Could lose information for one interrupt clear of interrupt #1, clears both #1 and #2 – Solution: disable interrupts • Disabling interrupts is a protected operation – Only the kernel can execute it – user v. s. kernel mode – mode bit in CPU status register • Other protected operations – installing interrupt handlers – manipulating CPU state (saving/restoring status registers) • Changing modes – interrupts – system calls (trap instruction) 25 CPS 110

CPU Handles Interrupt (with User Code) – CPU stops current operation, goes into kernel mode, saves current program counter and other processor state needed to continue at interrupted instruction. – Accessing vector table, in memory, jump to address of appropriate interrupt service routine for this event. – Handler does what needs to be done. – Restores saved state at interrupted instruction. Returns to user mode. 26 CPS 110

Multiple User Programs • Sharing system resources requires that we protect programs from other incorrect programs. – protect from a bad user program walking all over the memory space of the OS and other user programs (memory protection). – protect from runaway user programs never relinquishing the CPU (e. g. , infinite loops) (timers). – preserving the illusion of non-interruptable instruction sequences (synchronization mechanisms - ability to disable/enable interrupts, special "atomic" instructions). 27 CPS 110

CPU Handles Interrupt (Multiple Users) – CPU stops current operation, goes into kernel mode, saves current program counter and other processor state needed to continue at interrupted instruction. – Accessing vector table, in memory, jump to address of appropriate interrupt service routine for this event. – Handler does what needs to be done. – Restores saved state at interrupted instruction (with multiple processes, it is the saved state of the process that the scheduler selects to run next). Returns to user mode. 28 CPS 110

Timer Operation • Timer set to generate an interrupt in a given time. • OS uses it to regain control from user code. – Sets timer before transferring to user code. – when time expires, the executing program is interrupted and the OS is back in control. • Setting timer is privileged. 29 CPS 110

Issues of Sharing Physical Memory Protection: • Simplest scheme uses base and limit registers, loaded by OS (privileged operation) before starting program. • Issuing an address out of range causes an exception. base Running program limit Significance? 30 CPS 110

Allocation • Disjoint programs have to occupy different cells in memory (or the same cells at different times - swapping*) • Memory management has to determine where, when, and how** code and data are loaded into memory Running program Ready program * Where is it when it isn’t in memory? Memory Hierarchy **What HW support is available in architecture? CPS 110 31 MMU

Memory Hierarchy 101 Very fast 1 ns clock Multiple Instructions per cycle “CPU-DRAM gap” memory system architecture (CPS 104) P SRAM, Fast, Small Expensive $ Memory “I/O bottleneck” VM and file caching (CPS 110) DRAM, Slow, Big, Cheap (called physical or main) Magnetic, Really Slow, Really Big, Really Cheap => Cost Effective Memory System (Price/Performance) 32 CPS 110

Memory Hierarchy 101 P 95% hit in cache 1 ns 60 ns SRAM, Fast, Small Expensive $ Memory DRAM, Slow, Big, Cheap (called physical or main) Magnetic, Really Slow, Really Big, Really Cheap 15 ms What’s the ave. memory access time? 33 CPS 110

Role of MMU Hardware and OS • VM address translation must be very cheap (on average). – Every instruction includes one or two memory references. » (including the reference to the instruction itself) • VM translation is supported in hardware by a Memory Management Unit or MMU. – The addressing model is defined by the CPU architecture. – The MMU itself is an integral part of the CPU. • The role of the OS is to install the virtual-physical mapping and intervene if the MMU reports a violation. 34 CPS 110

Virtual Address Translation 29 Example: typical 32 -bit architecture with 8 KB pages. 00 Virtual address translation maps a virtual page number (VPN) to a physical page frame number (PFN): the rest is easy. virtual address VPN 0 13 offset address translation Deliver exception to OS if translation is not valid and accessible in requested mode. physical address { PFN + offset 35 CPS 110

Page Table Mapping Virtual page number Offset Page table ptr Page + TLB serves as a cache of PT entries. Page Table in memory Physical Memory CPS 110 36

Concurrency • Multiple things happening simultaneously – logically or physically • Causes – Interrupts – Voluntary context switch (system call/trap) – Shared memory multiprocessor P P Memory 37 CPS 110

The Trouble with Concurrency Time • Two threads (T 1, T 2) in one address space or two processes in the kernel • One counter T 1 T 2 ld (count) add switch ld (count) add st (count+1) count ld r 2, count add r 1, r 2, r 3 st count, r 1 count+1 switch st (count+1) count+1 count Shared Data 38 CPS 110

Solution: Atomic Sequence of Instructions Time T 1 begin atomic ld (count) add switch st (count+1) end atomic switch T 2 count begin atomic wait count+1 ld (count+1) add st (count+2) end atomic count+2 • Atomic Sequence – Appears to execute to completion without any intervening operations 39 CPS 110

HW Support for Atomic Operations • Could provide direct support in HW – Atomic increment – Insert node into sorted list? ? • Just provide low level primitives to construct atomic sequences – called synchronization primitives LOCK(counter->lock); counter->value = counter->value + 1; UNLOCK(counter->lock); • test&set (x) instruction: returns previous value of x and sets x to “ 1” LOCK(x) => while (test&set(x)); UNLOCK(x) => x = 0; 40 CPS 110

Summary • Fetch, Execute Cycle thread of control, indivisible operations, dynamic memory reference behavior • Execution Context what needs saved on context switch • Exceptions and Interrupts what drives OS • Mode bit, Privileged Instructions kernel structure • Memory Hierarchy MMU, access characteristics of levels • Concurrency atomic sequences, synchronization 41 CPS 110