Optimization of MultiValued MultiLevel Networks MVSIS Group Minxi

Optimization of Multi-Valued Multi-Level Networks MVSIS Group Minxi Gao, , Jie-Hong Jiang, Yunjian Jiang, Yinghua Li, Alan Mishchenko 1, Subarna Sinha, Tiziano Villa 2, and Robert Brayton Dept. of Electrical Engineering and Computer Science University of California, Berkeley 1 2 Portland State Univ. , Portland OR Parades, Rome, Italy

Outline Motivations: From binary to multi-value MV Networks & Design specification MVSIS optimizations n n Node simplification Algebraic extraction Pairing merging and encoding Network manipulations Demo New capabilities Conclusions

Motivations Synchronous binary hardware synthesis Software synthesis from synchronous specifications Asynchronous hardware synthesis Multi-valued devices? n n Current-mode CMOS devices Optical logic circuits

Motivation – synchronous hardware Design and synthesis from multi-valued logic n n MV is natural method of specification Larger design space Verilog-MV vl 2 mv BLIF-MV Two-level MV-PLA synthesis R. Rudell, et al “Espresso-MV”, 1987 FSM state encoding T. Villa, et al, “Nova”, 1990 E. Goldberg, et al, “Minsk”, 1999 Multi-level FSM synthesis (single MV) L. Lavagno, et al “MIS-MV”, 1990 MV-Optimize Opt-Encode MVSIS 1. 1 SIS Verilog

Motivation – software synthesis Synchronous programming of embedded systems n n n Esterel/Lustre/Signal Interactive FSM semantics Code generation from logic EFSM’s POLIS F. Balerin, et al, “Synthesis of software programs for embedded control applications”, TCAD 1999 ESTEREL G. Berry, “The foundations of Esterel”, 2000 MV-Optimize Code Gen MVSIS 1. 1 MVSIS Y. Jiang, et al, “Logic optimization and code generation for embedded control applications”, CODES 2000 POLIS VCC C/Assembly

Motivation – multi-valued devices Multi-valued current-mode MOS n n signed digit arithmetic High-speed, Low supply voltage Current source vm m Linear sum x y Building blocks PMOS current mirror Threshold detector Iy Ix IT x+y x y 1 y 2 T. Hanyu and M. Kameyama, “A 200 MHz pipelined multiplier using 1. 5 V-supply multiple-valued MOS current-mode circuits with dual-rail source-coupled logic”, IEEE Journal of Solid-Statee Circuits, 1995 A. Jain, R. Bolton and M. Abd El-Barr, “CMOS Multi-Valued Logic Design”, IEEE Trans. on Circuits and Systems, Aug. 1993.

Functional Semantics (MV-Network) F Network of MV-nodes Latch Each variable xn has its own range {0, 1, …, |pn|-1} Values are treated uniformly MV-literal: x{0, 2} MV-cube: x{0, 2}z{0, 1} MV-relation at each node (can be non-deterministic) Each output value is called an i-set F(u, v, w): {0, 1} x {0, 1, 2} 0 -set: F{0} = u{0} v{0} + u{0} v{1} w{0, 1} 2 -set: F{2} = u{1} v{1, 2} + u{1} v{0} w{1, 2} 1 -set: F{1} = <default>

Design Specification BLIF-MV subset n n Single output MV nodes Can be non-deterministic Flat network, no hierarchy (yet) Constant initial states (. reset) Extensions n External don’t care networks (. exdc) w Can have an external don’t care specified for each output n Can specify datapaths blif-mv. model simple. inputs a b. outputs f. mv f 3. mv x 3. table x a b -> f. def 0 0 1 1 1 {1, 2} 0 - 1 1 - 1 2 0 - 0 2. . reset x 0. latch f x. . exdc. inputs a b. outputs f. table a b -> f. def 0 0 0 1. end

MVSIS Optimization MVSIS optimizations n n n Node simplification Kernel and cube extraction/decomposition Pairing/Merging Encoding Network manipulations

MV-SOP Minimizers For each i-set (MV-input, binary output) n Two-level: Espresso-MV w minimize an i-set with a don’t care. w a don’t care is an input for which the output can be any value. n Two-Level: ISOP (Minato) w Fast method to build a cover of cubes of an iset from MDD of function and MDD of don’t cares (method of Minato extended to MV). All i-sets at once n Quine-Mc. Cluskey type ND minimization w Given a ND relation, generate a cover of all isets such that the total number of cubes is minimum. a 100 101 110 b 11 10 10 c 011 110 d 101 011 110 z 0 0 0 100 11 101 1 111 01 100 111 1 100 11 110 1 <default> 2 101 01 100 001 010 01 001 101 - DC

Node Simplification mvsis> simplify mvsis> fullsimp mvsis> reset_default Multi-level (using don’t cares - inputs for which output can be any value) n n Compatible observability don’t cares (CODC) Satisfiability don’t cares (SDC) External don’t cares (XDC) Generalization from binary case Q 1 Q 2. . . Qr Di Reference: Y. Jiang et. al. “Compatible Observable Don’t Cares for MV Logic, ICCAD’ 01 i image P 1 P 2. . . Pn care set DCi

Node Simplification mvsis> complete_simplify -m [ISOP, ESP, QM] Using non-determinism n n Derive Complete Flexibility at a node (an ND relation) Minimize ND relation w Espresso w ISOP w QM Automatically finds best default Uses external specification (relation) Reference: A. Mishchenko and R. Brayton, “Simplification of Non. Deterministic MV Networks”, IWLS, June 2002.

Z Computing Complete Flexibility at a node y j Yj X The complete flexibility at node j is

Quine-Mc. Cluskey type ND relation minimization P 0 minterms Given an ND relation, e. g. the complete flexibility, its i-set is the set of input minterms that can produce output value i. Generate for each i-set all its primes, Pi Form covering table with one column for each pj in Pi for all i One row for each minterm in the input space Solve minimum covering problem Primes chosen from each Pi is the cover for each i-set. P 1 P 2 P 3

Algebraic Decompositions Kernel extraction [-q]: Two-cube divisors [-g]: Best divisors Example: factoring/ decomposition/resub F = a{0, 1, 2} c{3} + b{1, 2, 3} c{3} + a{0}b{1, 2, 3} c{0} +a{0} c{1} Semi-algebraic division = (c{3} +a{0}c{0, 1}) (a{0, 1, 2} c{1, 3} +b{1, 2, 3} c{0, 3}) Resubstitution Factoring/Decomposition mvsis> fx [-q] [-g] resub decomp factor F M. Gao and R. K. Brayton, “Multi-valued Multi-level Network Decomposition”, IWLS, June 2001.

EBD Algebraic Decompositions mvsis> ebd_fx mvsis> ebd_decomp Stands for Encode, Binary, Decode Use binary codes to encode multi -valued variable x, e. g Operate with fast binary implementations imported from SIS J-H Jiang, A. Mishchenko, R. Convert (decode) back to multi-valued Brayton, Results: Quality almost as good, but much faster Example: Reducing Multi. Valued Operations to Binary, IWLS’ 02

Pairing Merging and Encoding Pair_decode/Merge n n Combine two or more nodes into a single node with more values. Explore different combinations a 100 101 110 b 11 10 10 c 011 110 d 101 011 110 <default> a x 0 0 0 full and partial encode Combine some i-sets n combine i-sets where those values always appear together in fanouts. mvsis> pair_decode mvsis> merge mvsis> encode c d y 100 11 011 101 0 101 10 111 0 <default> 1 1 merge Encode n b a b c d z 100 11 011 101 0 101 10 111 0 x 0 y 0 z 0 100 11 101 1 111 01 100 111 1 110 10 110 1 x 0 y 1 z 1 x 1 y 0 x 1 y 1 z 2 z 3 <empty> <default> 2 3

Other Commands Network manipulations n n n mvsis> eliminate mvsis> collapse mvsis> sweep IO interface n n mvsis> read(write)_blifmv mvsis> read(write)_blif Verification n n mvsis> validate -n # (uses simulation) mvsis> verify mvsis> gen_vec mvsis> simulate mvsis> qcheck (quick check for ND network) Printing § § § mvsis> mvsis> print_stats print_factor print_range print_io print_value Sequential § mvsis> extract_seq_dc

Design Flow Typical design flow mvsis> source mvsis. script (general MV script) mvsis> encode -i mvsis> source mvsis. scriptb (keeps all nodes binary)

Example #1 Matrix multiplication (3 values) #2 X 2 matrix mult over the ring Z_3. model matmul. inputs a 11 a 12 a 21 a 22. inputs b 11 b 12 b 21 b 22. outputs c 11 c 12 c 21 c 22. mv a 11, a 12, a 21, a 22 3. mv b 11, b 12, b 21, b 22 3. mv c 11, c 12, c 21, c 22 3. table 0 0 0 1 0 2 0 2 1 0 1 1 1 … …. table 0 0 0 1 0 2 0 2 - a 11 a 12 b 11 b 21 c 11 - 0 - =b 21 0 0 1 2 2 1 - =b 11 0 0 1 1 2 2 0 1 a 12 b 22 c 12 - 0 - =b 22 0 0 1 2 2 1 1 0 - - =b 12 1 1 0 0 0 1 1 1 1 0 2 2 … …. table a 21 a 22 b 11 b 21 c 21 0 0 - - 0 0 1 - - =b 21 0 2 - 0 0 0 2 - 1 2 0 2 - 2 1 1 0 - - =b 11 1 1 0 0 0 1 1 1 1 0 2 2 1 1 1 0 1 1 1 2 0 2 1 1 2 1 0 1 1 2 2 1 1 2 0 0 0 1 2 1 2 0 2 1 1 2 1 0 1 1 2 1 1 0 … … . table c 22 0 0 0 1 0 2 0 2 1 0 1 1 1 … …. end a 21 a 22 b 12 b 22 0 1 2 0 0 =b 22 0 2 1 =b 12 0 1 2 1

Demo 1. simulated 2. live

[cadntws 11: /home/wjiang/mvsis/examples/bob] mvsis UC Berkeley, MVSIS mvsis> help alias chng_name collapse decomp delete echo elim_part eliminate encode extract_seq_dc factor fullsimp fx gen_vec help history merge pair_decode print_altname print_factor print_io print_level print_part_value print_range print_stats print_value qcheck quit read_blifmv reset_default reset_name resub runtime set simplify simulate source sweep unalias undo unset usage validate write_blifmv mvsis> read_blifmv matmul-c mvsis> chng_name changing to short-name mode mvsis> print_stats matmul: 4 nodes, 4 POs, 128 cubes(sop), 480 lits(sop) mvsis>

mvsis> print_io primary inputs: a b c d e f g h primary outputs: {i} {j} {k} {l} mvsis> set autoexec pfs matmul: 4 nodes, 4 POs, 128 cubes(sop), 480 lits(sop), 216 lits(fact. ) mvsis> print_range {i}: 3 {j}: 3 {k}: 3 {l}: 3 a: 3 b: 3 c: 3 d: 3 e: 3 f: 3 g: 3 h: 3 matmul: 4 nodes, 4 POs, 128 cubes(sop), 480 lits(sop), 216 lits(fact. ) mvsis> simplify matmul: 4 nodes, 4 POs, 96 cubes(sop), 320 lits(sop), 160 lits(fact. ) mvsis> reset_default matmul: 4 nodes, 4 POs, 96 cubes(sop), 320 lits(sop), 160 lits(fact. ) mvsis>

mvsis> fullsimp matmul: 4 nodes, 4 POs, 96 cubes(sop), 320 lits(sop), 160 lits(fact. ) mvsis> pair_decode 1 m{0} = a{0}e{2} + e{0} m{1} = a{0}e{1} m{3} = a{1}e{2} + a{2}e{1} n{0} = a{0}f{2} + f{0} n{1} = a{0}f{1} n{3} = a{1}f{2} + a{2}f{1} o{0} = e{0}c{2} + c{0} o{1} = e{0}c{1} o{3} = e{1}c{2} + e{2}c{1} p{0} = f{0}c{2} + c{0} p{1} = f{0}c{1} p{3} = f{1}c{2} + f{2}c{1} q{0} = b{0}g{2} + g{0} q{1} = b{0}g{1} q{3} = b{1}g{2} + b{2}g{1} r{0} = b{0}h{2} + h{0} r{1} = b{0}h{1} r{3} = b{1}h{2} + b{2}h{1} s{0} = g{0}d{2} + d{0} s{1} = g{0}d{1} s{3} = g{1}d{2} + g{2}d{1} t{0} = h{0}d{2} + d{0} t{1} = h{0}d{1} t{3} = h{1}d{2} + h{2}d{1} matmul: 12 nodes, 4 POs, 64 cubes(sop), 184 lits(sop), 160 lits(fact. ) mvsis>

mvsis> simplify matmul: 12 nodes, 4 POs, mvsis> reset_default matmul: 12 nodes, 4 POs, mvsis> fullsimp matmul: 12 nodes, 4 POs, mvsis> 56 cubes(sop), 96 lits(sop), 96 lits(fact. ) 56 cubes(sop), 96 lits(fact. )

mvsis> print_factor {i}{1} = m{2}q{2} + m{1}q{0} + {i}{2} = m{2}q{0} + m{1}q{1} + {j}{1} = n{2}r{2} + n{1}r{0} + {j}{2} = n{2}r{0} + n{1}r{1} + {k}{1} = o{2}s{2} + o{1}s{0} + {k}{2} = o{2}s{0} + o{1}s{1} + {l}{1} = p{2}t{2} + p{1}t{0} + {l}{2} = p{2}t{0} + p{1}t{1} + m{0} = a{0} + e{0} m{2} = a{2}e{1} + a{1}e{2} n{0} = a{0} + f{0} n{2} = a{2}f{1} + a{1}f{2} o{0} = c{0} + e{0} o{2} = c{2}e{1} + c{1}e{2} p{0} = c{0} + f{0} p{2} = c{2}f{1} + c{1}f{2} q{0} = b{0} + g{0} q{2} = b{2}g{1} + b{1}g{2} r{0} = b{0} + h{0} r{2} = b{2}h{1} + b{1}h{2} s{0} = d{0} + g{0} s{2} = d{2}g{1} + d{1}g{2} t{0} = d{0} + h{0} t{2} = d{2}h{1} + d{1}h{2} matmul: 12 nodes, 4 POs, 56 mvsis> m{0}q{1} m{0}q{2} n{0}r{1} n{0}r{2} o{0}s{1} o{0}s{2} p{0}t{1} p{0}t{2} cubes(sop), 96 lits(fact. )

mvsis> validate -m mdd matmul-c Networks are combinationally equivalent according to MDD method. matmul: 12 nodes, 4 POs, 56 cubes(sop), 96 lits(fact. ) mvsis>

[cadntws 11: /home/wjiang/mvsis/examples/bob] mvsis UC Berkeley, MVSIS mvsis> read_blifmv red-add. mv mvsis> chng_name changing to short-name mode mvsis> print_io primary inputs: a b c d e primary outputs: {f} {g} {h} mvsis> set autoexec pfs red_adder: 3 nodes, 3 POs, 48 cubes(sop), 240 lits(sop), 69 lits(fact. ) mvsis> reset_default red_adder: 3 nodes, 3 POs, 48 cubes(sop), 240 lits(sop), 69 lits(fact. ) mvsis> simplify red_adder: 3 nodes, 3 POs, 15 cubes(sop), 44 lits(sop), 28 lits(fact. ) mvsis> fullsimp red_adder: 3 nodes, 3 POs, 15 cubes(sop), 44 lits(sop), 28 lits(fact. ) mvsis>

mvsis> print_range {f}: 2 {g}: 2 {h}: 2 a: 8 b: 8 c: 8 d: 8 e: 8 red_adder: 3 nodes, mvsis> 3 POs, 15 cubes(sop), 44 lits(sop), 28 lits(fact. ) mvsis> encode red_adder: 3 nodes, mvsis> 3 POs, 15 cubes(sop), 44 lits(sop), 28 lits(fact. ) mvsis> print_range {f}: 2 {g}: 2 {h}: 2 i: 2 j: 2 k: 2 l: 2 m: 2 n: 2 red_adder: 3 nodes, mvsis> o: p: q: r: s: t: u: v: w: 3 POs, 2 2 2 2 2 15 cubes(sop), 44 lits(sop), 28 lits(fact. )

mvsis> simplify red_adder: 3 nodes, mvsis> fullsimp red_adder: 3 nodes, mvsis> print_io primary inputs: i j primary outputs: {f} red_adder: 3 nodes, mvsis> 3 POs, 15 cubes(sop), 44 lits(sop), 28 lits(fact. ) k l m n o p q r s t u v w {g} {h} 3 POs, 15 cubes(sop), 44 lits(sop), 28 lits(fact. )

mvsis> read_blifmv red-add. mv red_adder: 3 nodes, 3 POs, 48 cubes(sop), mvsis> help encode 240 lits(sop), 69 lits(fact. ) Feb 16, 2001 MVSIS(1) encode [-i] [-n] [-s] Encode the whole network into a binary one, considering both output and input constraints. For sequential networks, a latch is encoded with constraints generated from both its inputs and outputs -i keep primary inputs and outputs as multi-valued; add interface nodes between the internal encoded binary network and PI/POs. This option allows validation of the result. -n use natural code -s use NO_COMP rather than ESPRESSO as the intermediate minimization method. The difference is only in performance. Ordinary users should not be concerned with this option. red_adder: 3 nodes, mvsis> encode -n red_adder: 3 nodes, mvsis> 3 POs, 48 cubes(sop), 240 lits(sop), 3 POs, 1251 cubes(sop), 69 lits(fact. ) 9432 lits(sop), 577 lits(fact. )

mvsis> simplify -t 1000 red_adder: 3 nodes, 3 POs, 315 cubes(sop), 2010 lits(sop), mvsis> simplify -t 1000 -m exact red_adder: 3 nodes, 3 POs, 300 cubes(sop), 1989 lits(sop), mvsis> validate -m mdd red-add-bin. mv Networks differ on (at least) primary output s 1 i-set 0 Incorrect input is: 0 x 1_b 0 1 x 1_b 1 1 x 1_b 2 0 x 0_b 0 0 x 0_b 1 0 x 0_b 2 0 y 1_b 0 0 y 1_b 1 0 y 1_b 2 0 y 0_b 0 0 y 0_b 1 0 y 0_b 2 0 cin_b 0 0 cin_b 1 0 cin_b 2 Networks are NOT combinationally equivalent. red_adder: 3 nodes, 3 POs, 300 cubes(sop), mvsis> 1989 lits(sop), 156 lits(fact. ) 130 lits(fact. )

New Capabilities Non-deterministic MV Networks Post Networks Delay Insensitive Asynchronous Synthesis

Conclusions MV logic networks important in various applications Presented MVSIS, an multi-valued logic synthesis software infrastructure Release 1. 1 on Linux and Windows platforms (as of May, 2002) n Support registers n External and sequential don’t cares n Verification based on MDD representations n software generation from Esterel n use of complete flexibility n non-determinism http: //www-cad. eecs. berkeley. edu/Respep/Research/mvsis free download (binary versions available on Windows, Unix)

Some Recent Publications Multi-Valued Logic Optimization on Post Logic Networks submitted to ICCAD 2002 Simplification of Non. Deterministic Multi-Valued Networks IWLS 2002 Don’t Care Computations in Minimizing Extended Finite State Machines with Presburger Arithmetic IWLS 2002 A Boolean Paradigm in Multi. Valued Logic Synthesis IWLS 2002 Software Synthesis from Synchronous Specifications Using Logic Simulation Techniques DAC 2002

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