NTU GIEE EECS VLSI Crash Course Synthesis LiYang

NTU GIEE EECS VLSI Crash Course Synthesis Li-Yang Huang Jul. 18, 2019

NTU GIEE EECS Reference u VLSI Crash Course Synthesis 2018 Yi-Long Liou 2

NTU GIEE EECS Outline u Introduction u Synopsys Graphical Environment u DC-TCL: Introduction u Setting Design Environment u Setting Design Constraints u Synthesis Report and Analysis u Gate-Level Simulation 3

NTU GIEE EECS Outline u Introduction u Synopsys Graphical Environment u DC-TCL: Introduction u Setting Design Environment u Setting Design Constraints u Synthesis Report and Analysis u Gate-Level Simulation 4

NTU GIEE EECS Cell-Based Design Flow Implenentation Logic synthesis Verification RTL code always @ (posedge clk) if (in 1==1) a=c+d else a=c-d Gate-Level netlist RTL Simulation Lint check code coverage analysis Formal Gate level Simulation Static Timing Analysis Power Analysis Place&Route Post layout Gate-Level netlist Formal Gate level Simulation Static Timing Analysis Power Analysis transistor netlist LVS GDS layout Extraction DRC Tape out Transistor-level Simulation Transistor-level STA Power Analysis 5

NTU GIEE EECS Synthesis Design Flow u u Develop the HDL design description and simulate the design description to verify that it is correct Set up the. synopsys_dc. setup file. l l u u l l RTL Coding Prepare Set the appropriate technology, synthetic, and symbol libraries, target libraries, and link libraries. Set the necessary compilation options, including options to read in the input files and specify the output formats. Read the HDL design description Define the design. l Specification Set design attributes Define environmental conditions Set design rules Set realistic constraints (timing and area goals) Determine a compile methodology Cell Library Setting Design Environment Setting Design Constraint Compile Design Analysis Gate-level Cell-based Netlist 6

NTU GIEE EECS What is Synthesis u source /usr/cad/synopsys/CIC/synthesis. cshrc 7

NTU GIEE EECS What is Synthesis u Synthesis = translation + optimization + mapping 8

NTU GIEE EECS Logic Synthesis Overview c=a+b + - x / cos sin 9

NTU GIEE EECS HDL Compiler u In schematic view, we can see the Verilog file is translated into Design Compiler as Synopsys design block with a GTECH library (the Synopsys default) always @(reset or set) begin if (reset) y=1'b 0; else if (set) y=1'b 1; end always @(gate or reset) begin if (reset) t=1'b 0; else if (gate) t=d; end HDL Comipler 10

NTU GIEE EECS Design Compiler u Design Compiler maps Synopsys design block to gate level design with a user specified library Technology Library 11

NTU GIEE EECS Design Compiler Interaction u Three ways to interface Design Vision (GUI) dc_shell (Legacy Interface) GUI Design Compiler (DC) dc_shell –t (TCL Interface) Command line 12

NTU GIEE EECS RTL Coding Related to Synthesis u Syntax l l Each-variable is assigned in the same always block Delay is for simulation, not for synthesis l u Synopsys full_case / parallel_case Partition for synthesis l l l u Memory case: #1 in nonblocking block v. s +notimingcheck Separate combinational and sequential part Separate control and VLSI-design strategy Register at input/output Special-case needs constraint setting l l Clock gating Multi-cycle False path Asynchronous logic 13

NTU GIEE EECS STA (Static Timing Analysis) u Sequential circuits are usually constrained by clock specify l l Clock cycle >= DFFclk-Qdelay + combinational delay + DFFsetup DFFclk-Qdelay + combinational delay >= DFFhold 1. CLK pin of Flop 1 to D pin of Flop 2 2. Input port to a D pin of Flop. 3. Q pin of flop to an output port 4. Input to output port through purely combinational logic 14

NTU GIEE EECS Trade-off between Speed and Area u Synthesis is Constraint Driven u Technology Independent 15

NTU GIEE EECS What. synopsys_dc. setup Defined u u u search_path: the path to search for unsolved reference library or design target_library: the ASIC technology that the design is mapped to link_library: the library used for interpreting input description l l Any cells instantiated in your HDL code Wire Load or Operating Condition models used during synthesis u symbol_library: used during schematic generation synthetic_library: designware library to be used u Other variables u 16

NTU GIEE EECS Synopsys Related Files u Set your. synopsys_dc. setup set company "EECS“ set designer "Student“ set search_path “. $Your_path/CBDK_TSMC 018/Synopsys. DC/db/ . /Memory/ $search_path“ set target_library “ slow. db fast. db tpz 973 gvwc. db tpz 973 gvbc. db SRAM 2048 x 20_slow_syn. db SRAM 2048 x 20_fast_syn. db “ set link_library “ * $target_library dw_foundation. sldb “ set symbol_library “ tsmc 18. sdb generic. sdb “ set synthetic_library “ dw_foundation. sldb “ set verilogout_no_tri true set hdlin_enable_presto_for_vhdl "TRUE“ set sh_enable_line_editing true keep 100 alias h history 17

NTU GIEE EECS Outline u Introduction u Synopsys Graphical Environment u DC-TCL: Introduction u Setting Design Environment u Setting Design Constraints u Synthesis Report and Analysis u Gate-Level Simulation 18

NTU GIEE EECS Invoke Design Vision u Linux%> dv & 19

NTU GIEE EECS Optimization Using the Design Vision u u u u File/Read or File/Analyze & File/Elaborate Attributes – set up Design Environment & Goals (record in script sdc files) Analysis/Report - check if set up is OK Analysis/Check Design Tools/Design Optimization Analysis/Report File/Save 20

NTU GIEE EECS Read File u u u Read netlists or other design descriptions into Design Compiler File/Read Support many different formats: l l l Verilog: . v VHDL: . vhd System Verilog: . sv EDIF PLA(Berkeley Espresso): . pla Synopsys internal formats DB(binary): . db equation: . eqn state table: . st Equivalent dc_shell command : dc_shell> read_file –format verilog lab 1. v 21

NTU GIEE EECS Analyze & Elaborate u u u Use analyze and elaborate to bring Verilog or VHDL files into design compiler memory Analyze does syntax checking and produces an intermediate. syn. mr. pvl files to be stored in a design library Elaborate looks in the design library for the intermediate file and builds the design up into design compiler memory (as design block) 22

NTU GIEE EECS Analyze File/Analyze u u Check VHDL & Verilog for syntax and synthesizability Create intermediate. syn. mr. pvl files and places them in library specified – design library Equivalent dc_shell command : dc_shell> analyze -format verilog –library WORK counter. v 23

NTU GIEE EECS Elaborate u u Elaborate after analyze to bring design into Design Compiler memory using generic components (GTECH) Look in the design library for intermediate file for design specified File/Elaborate Equivalent dc_shell command : dc_shell> elaborate counter -architecture verilog -library WORK 24

NTU GIEE EECS Describe the Design Environment u You can use Design Vision to constrain your design 25

NTU GIEE EECS Link Design u u u Analysis/Link Design Execute link -all before you optimize your design To ensure all sub-elements of your hierarchical design are available 26

NTU GIEE EECS Check Design u Analysis/Check Design u Execute check_design before you optimize your design Two types of messages are issued Error u u Error: In design ‘bcd 7 segs’, cell ‘decoder’ has more pins than it’s reference ‘d 1’ has ports Warnings l u l Warning: In design ‘converter’, port ‘A’ is not connected to any nets 27

NTU GIEE EECS Compile the Design u The compile command optimizes and maps the current_design 28

NTU GIEE EECS Report the Design u From Design report and Timing analysis, you can find the set attributes and the results after optimization 29

NTU GIEE EECS Outline u Introduction u Synopsys Graphical Environment u DC-TCL: Introduction u Setting Design Environment u Setting Design Constraints u Synthesis Report and Analysis u Gate-Level Simulation 30

NTU GIEE EECS DC-TCL(Tool Command Language) u u u TCL script = sequence of commands l. synopsys_setup / my_script. tcl / DUT_syn. sdc l Separate line ; Comments # GUI interface v. s. DC-TCL command l dv –f script. tcl TCL Basics dc_shell>help get_* l Function arguments l Variable Substitution l Syntax: $var. Name (set a b v. s set a $b) Nested Commands u Return string result Syntax: [commands. . ] (set a “b-3 is [expr $b-3]”) get_, all_ command syntax l Search the current design for names of the given object types Syntax: [get_type [-hierarchy] [name_list]] (set_dont_touch [get_cells * -hier]) [all_inputs]… 31

NTU GIEE EECS Design Objects u u u u Design: A circuit that performs one or more logical functions Cell: An instance of a design or library primitive within A design Reference: The name of the original design that a cell instance “points to” Port: The input or output of a cell Pin: input or output of a design Net: The wire that connects ports to pins and/or pins to each other Clock: Waveform applied to a port or pin identified as a clock source 32

NTU GIEE EECS Design Objects Module TOP(A, B, C, D, CLK, OUT 1); input A, B, C, D, CLK; clock output [1: 0] OUT 1; port wire INV 0, INV 1, BUS 0, BUS 1; ENCODER U 1 (. AIN(A), . BIN(B), . CIN(C), . DIN(D), . Q 0(BUS 0), . Q 1(BUS 1)); INV U 2 (. A(BUS 0, . Z(INV 0))), pin U 3 (. A(BUS 1, . Z(INV 1))); REGFILE U 4(. D 0(INV 0), . D 1(INV 1), . CLK(CLK), . Q[0](OUT[0]), . Q[1](OUT[1])); endmodule cell reference and design pin cannot appear by itself, must accompany with cell 33

NTU GIEE EECS Design Objects Exercise pin cannot appear by itself, must accompany with cell u u u Make a list of all the ports in the design? { get_ports A, B, CLK, SUM } Make a list of all the cells that have the letter “U” in their name? { get_cells *U* ADDER/U 1, DFF/U 2 } Make a list of all the nets ending with “CLK”? { get_nets *CLK } Make a list of all the “Q” pins in the design? { get_pins */Q U 2/Q } Make a list of all the references? { ADDER, DFF } 34

NTU GIEE EECS Outline u Introduction u Synopsys Graphical Environment u DC-TCL: Introduction u Setting Design Environment u Setting Design Constraints u Synthesis Report and Analysis u Gate-Level Simulation 35

NTU GIEE EECS Why Describes the Real World Environment u Beware that the defaults are not realistic conditions l l l u u Input drive is not infinite Capacitive loading is usually not zero Consider process, temperature, and voltage (PVT) variation The operating environment affects the components selected from target library and timing through your design. The real world environment you define describes the conditions that the circuit will operate within. 36

NTU GIEE EECS Describing Design Environment (1/2) 1 set_operating_conditions 4 3 set_driving_cell 5 set_load set_input_delay set_wire_load_model create_clock 2 6 set_output_delay 37

NTU GIEE EECS Describing Design Environment (2/2) For STA, every node should be known: • RC value • Inside DUT: Tech lib 1. standard cell/external-IP 2. wire load model • Outside DUT: • set_drive / set_driving_cell • set_load • I/O delay • set_input_delay • set_output_delay 38

NTU GIEE EECS 1. Setting Operating Condition u Attributes/Operating Environment/Operating Condition Step 1 Step 2 Name Process Temp Volt Slow 1 125 1. 62 Typical 1 25 1. 8 Fast 1 -40 1. 98 Equivalent dc_shell command : dc_shell> set_operating_conditions -max_library slow -max slow -min_library fast -min fast 39

NTU GIEE EECS 2. Setting Wire Load Model u u Wire load model estimates wire capacitance based on chip area & cell fanout Attributes/Operating Environment/Wire Load Step 1 Step 2 Equivalent dc_shell command : dc_shell> set_wire_load_model –name tsmc 18_w 10 –library slow 40

NTU GIEE EECS Drive Strength & Load for Pads u Input Drive Strength for Pads u Output Load for Pads 41

NTU GIEE EECS 3. & 4. Input Drive Strength & Output Loading u Consider for IO Pads (Synthesis w IO) u Setting Input Drive Strength TSMC 18: PDIDGZ R pad c dc_shell command : dc_shell> set_driving_cell –library tpz 973 gvwc –lib_cell PDIDGZ –pin {C} [all_inputs] u Setting Output Loading dc_shell command : dc_shell> set_load [load_of “tpz 973 gvwc/PDT 16 DGZ/I” ] [all_outputs] u Remember to add IO. db into target_library in. synopsys_setup 42

NTU GIEE EECS Port Report u Design/Reports Step 1 Step 2 dc_shell command : dc_shell> report_port -verbose {port_list } 43

NTU GIEE EECS STA (Static Timing Analysis) u Sequential circuits are usually constrained by clock specify l l Clock cycle >= DFFclk-Qdelay + combinational delay + DFFsetup DFFclk-Qdelay + combinational delay >= DFFhold 1. CLK pin of Flop 1 to D pin of Flop 2 2. Input port to a D pin of Flop. 3. Q pin of flop to an output port 4. Input to output port through purely combinational logic 44

NTU GIEE EECS Input/Output Delay u Clock cycle >= DFFclk-Qdelay + c + DFFsetup u Clock cycle >= DFFclk-Qdelay + a + b + DFFsetup Input delay = DFFclk-Qdelay + a u u u Clock cycle >= DFFclk-Qdelay + d + e + DFFsetup Output delay = e + DFFsetup 45

5. Setting Input Delay u u Select input ports Attributes/Operating Environment/Input Delay l Step 1 NTU GIEE EECS Attention! The step should execute after clock specify Relative to clock trigger time Step 3 Step 2 Equivalent dc_shell command : dc_shell> set_input_delay –clock clk –max 6. 4 [get_ports in 1] dc_shell> set_input_delay –clock clk –min 4. 4 [get_ports in 1] 46

6. Setting Output Delay u u NTU GIEE EECS Attention! The step should execute after clock specify Select output ports Attributes/Operating Environment/Output Delay l Relative to clock trigger time Step 3 Step 2 Step 1 Equivalent dc_shell command : dc_shell> set_output_delay –clock clk –max 5. 3 [get_ports out 1] dc_shell> set_output_delay –clock clk –min 4. 4 [get_ports out 1] 47

NTU GIEE EECS SDC about Setting Design Environment set cycle 20 set t_in [expr $cycle/2] set t_out 0. 5 # Constraint setting # Clock constraints create_clock -name clk -period $cycle [get_ports clk] set_fix_hold [get_clocks clk] set_dont_touch_network [get_clocks clk] set_ideal_network [get_ports clk] set_clock_uncertainty 0. 1 [get_clocks clk] 0. 5 [get_clocks clk] set_clock_latency # Other constraints set_max_fanout 6 [all_inputs] 1 2 3 4 5 6 # Environment setting set_operating_conditions -min_library fast -min fast -max_library slow -max slow set_wire_load_model -name tsmc 13_wl 10 -library slow set_drive 1 [all_inputs] set_load 1 [all_outputs] set_input_delay $t_in -clock clk [remove_from_collection [all_inputs] [get_ports clk]] set_output_delay $t_out -clock clk [all_outputs] 48

NTU GIEE EECS Outline u Introduction u Synopsys Graphical Environment u DC-TCL: Introduction u Setting Design Environment u Setting Design Constraints l Optimization Constraints l Basic clock constraints concept Constraints & STA for Special Circuits Constraint for Power & Area Design Rule Constraint u Synthesis Report and Analysis u Gate-Level Simulation 49

NTU GIEE EECS Basic Clock Constraints u Clock七大法則: l l Period & Waveform Fix timing issue: u Uncertainty l u Skew Latency l l u Fix hold Issue handled in P&R CTS Stage Don’t touch Set ideal network (告知DC無skew問題, 之後利用uncertainty悲觀模擬解決) Source latency (option) Network latency Transition l Input transition l 測試機台環境→適用whole system情況 DUT is submodule: set driving strength Clock transition In P&R, 限制其後接的FF數 50

NTU GIEE EECS Specify Clock Constrains u Select clock port u Attributes/Specify Clock u create_clock : define clock’s waveform dc_shell> create_clock -name clk -period 10 -waveform {0 5} { clk } //2 nd clk: ports name u set_fix_hold : respect the hold time requirement of all clocked flip-flops Step 1 dc_shell> set_fix_hold [ get_clocks clk] Step 2 u set_dont_touch_network : do not re-buffer the clock network dc_shell> set_dont_touch_network [ get_clocks clk ] u set_ideal_network dc_shell> set_ideal_network [ get_ports clk ] 51

NTU GIEE EECS STA (Static Timing Analysis) u Sequential circuits are usually constrained by clock specify l l Clock cycle >= DFFclk-Qdelay + combinational delay + DFFsetup DFFclk-Qdelay + combinational delay >= DFFhold 1. CLK pin of Flop 1 to D pin of Flop 2 2. Input port to a D pin of Flop. 3. Q pin of flop to an output port 4. Input to output port through purely combinational logic 52

NTU GIEE EECS Clock Skew Issue Arrival(FF 1) = 0. 5 ns Arrival(FF 2) = 1. 2 ns Arrival(FF 1) = 1. 2 ns Arrival(FF 2) = 0. 5 ns 53

NTU GIEE EECS Setting Clock Uncertainty u Different clock arrival time l l l Models clock skew effects on the clock After CTS in P&R real propagated skew is considered! Experie Small circuits: 0. 1 ns Large circuits: 0. 3 ns Equivalent dc_shell command : dc_shell> set_clock_uncertainty 0. 1 [get_clocks clk] Timing report 54

NTU GIEE EECS Setting Clock Latency u Source latency u Network latency Equivalent dc_shell command : dc_shell> set_clock_latency –source 3 [get_clocks clk] dc_shell> set_clock_latency 1 [get_clocks clk] 55

Combinational Circuit –NTU GIEE EECS Max Delay Constraints u For combinational circuits only l l Select the start & end points of the timing path Attributes/Optimization Constraints/Timing Constraints Equivalent dc_shell command : dc_shell> set_max_delay 1 from [all_inputs] –to [all_outputs] 56

NTU GIEE EECS Setting Area & Power Constraint u Attributes/Optimization Constraints/Design Constraints Area unit(follow unit defined in library): 1. Equivalent gate counts Gate counts = Chip Report Area / NAND 2 Area 2. um x um 3. Transistors Equivalent dc_shell command : dc_shell> set_max_area 0 57

NTU GIEE EECS Design Rule Constraints u u u Design rules constraints can’t be violated at any cost, even if it will violate the timing and area goal Design rules constraints restrict how many cells are connected to one another based on capacitance, transition and fanout You may apply more conservative design rules to: l l u Anticipate the interface environment your block will see Prevent the design from operating cell close to their limits, where performance degrades rapidly Three kinds of design rule constraint are set: l set_max_transition set_max_fanout l set_max_capacitance l set_max_transition 0. 2 [get_ports IN 1] set_max_fanout 6 [get_ports IN 1] set_max_capacitance 2 [get_ports IN 1] 58

NTU GIEE EECS Constraints Priority u During the optimization, there exists a constraint priority relationship. l Design Rule Constraint (max_transition, max_fanout, max_capacitance) l l l u Timing constraint (max_delay, min_delay) Power constraint Area constraint Use set_cost_priority command to modify the order Equivalent dc_shell command : dc_shell> set_cost_priority [ -default] [-delay] [cost_list] EX : set_cost_priority {max_fanout max_capacitance max_delay} 59

NTU GIEE EECS SDC about Setting Design Constraint set cycle 20 set t_in [expr $cycle/2] set t_out 0. 5 # Constraint setting # Clock constraints create_clock -name clk -period $cycle [get_ports clk] set_fix_hold [get_clocks clk] set_dont_touch_network [get_clocks clk] set_ideal_network [get_ports clk] set_clock_uncertainty 0. 1 [get_clocks clk] 0. 5 [get_clocks clk] set_clock_latency # Other constraints set_max_fanout 6 [all_inputs] # Environment setting set_operating_conditions -min_library fast -min fast -max_library slow -max slow set_wire_load_model -name tsmc 13_wl 10 -library slow set_drive 1 [all_inputs] set_load 1 [all_outputs] set_input_delay $t_in -clock clk [remove_from_collection [all_inputs] [get_ports clk]] set_output_delay $t_out -clock clk [all_outputs] 60

NTU GIEE EECS Check Design u u After you set up the deign attributes & design constraints, we recommend the next step is to check design Analysis/Check Design l l Example: multiple instance How to handle ? uniquify 61

NTU GIEE EECS Uniquify u u u Create a unique design file for each instance May select one cell or entire design hierarchy to be uniquify Allow design to be customized to its interface Step 2 u Select the most top design of Step 1 the hierarchy u Hierarchy/Uniquify/Hierarchy Equivalent dc_shell command : dc_shell> uniquify 62

NTU GIEE EECS Check Constraints & Attributes u u Use the following reports to check constraints & attributes before compiling Deign/Report Constrants Step 2 Step 1 63

NTU GIEE EECS Save Constraints & Attributes u Save attributes & constraints setting as the design setup file in TCL command format u File/Save Info/Design Setup 64

NTU GIEE EECS Execute Script File u Execute TCL command script file, use u File/Execute Script Step 2 Step 1 Another method 65

NTU GIEE EECS Compile Step 1 Step 2 Equivalent dc_shell command : dc_shell> compile –exact_map –map_effort high –bounaray_optimization 66

NTU GIEE EECS Assign Problem u The syntax of “assign” may cause problems in the LVS Equivalent dc_shell command : dc_shell> set_fix_multiple_port_nets -all -buffer_constants 67

NTU GIEE EECS Floating Port Removing u Due to some ports in the standard cells are not used in your design Equivalent dc_shell command : dc_shell> remove_unconnected_ports -blast_buses [get_cells -hierarchical *] 68

NTU GIEE EECS Change Naming Rule u Purpose: Let the naming-rule definitions in the gate-level netlist are the same as in the timing file (e. g. *. sdf file) l Also, the wrong naming rules may cause problems in the LVS Bus[5] → Bus_5_ 69

NTU GIEE EECS Problem: High Fan-out Net u Report Timing Path l clock or reset has big delay 1. set hign_fanout_net_threshold 0 2. Find high fanout net l report_net_fanout –high_fanout l set_dont_touch_network set_ideal_network l l report_net_fanout –high_fanout compile –inc –map_effort high P 70

NTU GIEE EECS Outline u Introduction u Synopsys Graphical Environment u DC-TCL: Introduction u Setting Design Environment u Setting Design Constraints u Synthesis Report and Analysis u Gate-Level Simulation 71

NTU GIEE EECS Timing Report u Timing/Report Timing Path Step 2 Step 1 72

NTU GIEE EECS Timing Report (from STA) Start End 73

NTU GIEE EECS Area Report External IP Don’t care net area! 74

NTU GIEE EECS Outline u Introduction u Synopsys Graphical Environment u DC-TCL: Introduction u Setting Design Environment u Setting Design Constraints u Synthesis Report and Analysis u Gate-Level Simulation 75

NTU GIEE EECS Gate-Level Simulation (Verilog) u Write out gate-level netlist 1. File/Save As Verilog 2. u > write -format verilog -hierarchy -output chip_syn. v Get SDF(Standard Delay Format) > write_sdf –version 2. 1 chip_syn. sdf u Modify your testbench file to include timing delay(Back annotate) $sdf_annotate (“the_SDF_FILE_NAME”, top_module_instance_name); u Gate level simulation with timing information: >> ncverilog testbench. v chip_syn. v –v tsmc 18. v +access+r 76

NTU GIEE EECS Thanks for Listening